H8DT(DDAltera SOCFPGA VT!altr,socfpga-vtaltr,socfpgaaliases,/soc/serial0@ffc020004/soc/serial1@ffc03000HRdnand@ff900000!altr,socfpga-denali-nandrunand_datadenali_reg  -.nandnand_xecc $ %disabledsram@ffff0000 !mmio-sramr+spi@ff705000!!intel,socfpga-qspicdns,qspi-norrpP / % %disabledrstmgr@ffd05000 !altr,rst-mgrrPsnoop-control-unit@fffec000!arm,cortex-a9-scursdr@ffc25000!altr,sdr-ctlsysconrP =0sdramedac!altr,sdram-edac0 'spi@fff00000!snps,dw-apb-ssir 1 2spi %disabledspi@fff01000!snps,dw-apb-ssir 1 3spi %disabledsysmgr@ffd08000!altr,sys-mgrsysconrЀ@Ѐ%timer@fffec600!arm,cortex-a9-twd-timerr  2timer0@ffc08000!snps,dw-apb-timer r*timer *timer9jtimer1@ffc09000!snps,dw-apb-timer r*timer +timer9jtimer2@ffd00000!snps,dw-apb-timer r timer (timer9jtimer3@ffd01000!snps,dw-apb-timer r timer )timer9jserial0@ffc02000!snps,dw-apb-uartr  *33txrx 09pserial1@ffc03000!snps,dw-apb-uartr0 *33txrx 19pusbphy!!usb-nop-xceiv%okay5usb@ffb00000 !snps,dwc2r }4otg "dwc2,5 1usb2-phy %disabledusb@ffb40000 !snps,dwc2r 4otg #dwc2,5 1usb2-phy %disabledwatchdog@ffd02000 !snps,dw-wdtr    & %disabledwatchdog@ffd03000 !snps,dw-wdtr0   ' %disabledchosen;console=ttyS0,57600memory@0fmemoryr@ #address-cells#size-cellsmodelcompatibleserial0serial1timer0timer1timer2timer3enable-methoddevice_typeregnext-level-cachephandleinterrupt-parentinterruptsinterrupt-affinity#interrupt-cellsinterrupt-controllerranges#dma-cellsclocksclock-namesresetsreset-namesfpga-mgrstatus#clock-cellsclock-frequencydiv-regfixed-dividerclk-gateclk-phasesnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blenaltr,sysmgr-sysconinterrupt-namesmac-addresssnps,multicast-filter-binssnps,perfect-filter-entriestx-fifo-depthrx-fifo-depthsnps,axi-configphy-modegpio-controller#gpio-cellssnps,nr-gpiosiramcache-unifiedcache-levelarm,tag-latencyarm,data-latencyprefetch-dataprefetch-instrarm,shared-overridearm,double-linefillarm,double-linefill-incrarm,double-linefill-wraparm,prefetch-droparm,prefetch-offsetbroken-cdbus-widthcap-mmc-highspeedcap-sd-highspeedreg-namescdns,fifo-depthcdns,fifo-widthcdns,trigger-address#reset-cellsaltr,modrst-offsetaltr,sdr-sysconnum-cscpu1-start-addrreg-shiftreg-io-widthdmasdma-names#phy-cellsphysphy-namesbootargs