NHH(H1Altera SOCFPGA Cyclone V SoC Macnica Sodia board1!macnica,sodiaaltr,socfpga-cyclone5altr,socfpgaaliases,/soc/serial0@ffc020004/soc/serial1@ffc030002%/okayflash@0!micron,n25q512ajedec,spi-nor|Set22rstmgr@ffd05000 !altr,rst-mgr|Psnoop-control-unit@fffec000!arm,cortex-a9-scu|sdr@ffc25000!altr,sdr-ctlsyscon|P=3sdramedac!altr,sdram-edac3 'spi@fff00000!snps,dw-apb-ssi|  42spi /disabledspi@fff01000!snps,dw-apb-ssi|  43spi /disabledsysmgr@ffd08000!altr,sys-mgrsyscon|Ѐ@Ѐ%timer@fffec600!arm,cortex-a9-twd-timer|  5timer0@ffc08000!snps,dw-apb-timer |+timer*timertimer1@ffc09000!snps,dw-apb-timer |+timer+timertimer2@ffd00000!snps,dw-apb-timer | timer(timertimer3@ffd01000!snps,dw-apb-timer | timer)timerserial0@ffc02000!snps,dw-apb-uart|  ",+966>txrx0serial1@ffc03000!snps,dw-apb-uart|0 ",+966>txrx1usbphyH!usb-nop-xceiv/okay8usb@ffb00000 !snps,dwc2| }7otg"dwc2S8 Xusb2-phy /disabledusb@ffb40000 !snps,dwc2| 7otg#dwc2S8 Xusb2-phy/okaywatchdog@ffd02000 !snps,dw-wdt|   &/okaywatchdog@ffd03000 !snps,dw-wdt|0  ' /disabledchosen bearlyprintkkserial0:115200n8memory@0pmemory|@regulator!regulator-fixedw3.3V2Z2Z/gpio-leds !gpio-ledshps_led0hps:green:led0 . hps_led1hps:green:led1 . hps_led2hps:green:led2 .hps_led3hps:green:led3 . #address-cells#size-cellsmodelcompatibleserial0serial1timer0timer1timer2timer3ethernet0enable-methoddevice_typeregnext-level-cachephandleinterrupt-parentinterruptsinterrupt-affinity#interrupt-cellsinterrupt-controllerranges#dma-cellsclocksclock-namesresetsreset-namesfpga-mgrstatus#clock-cellsclock-frequencydiv-regfixed-dividerclk-gateclk-phasesnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blenaltr,sysmgr-sysconinterrupt-namesmac-addresssnps,multicast-filter-binssnps,perfect-filter-entriestx-fifo-depthrx-fifo-depthsnps,axi-configphy-modephyrxd0-skew-psrxd1-skew-psrxd2-skew-psrxd3-skew-psrxdv-skew-psrxc-skew-pstxen-skew-pstxc-skew-psgpio-controller#gpio-cellssnps,nr-gpiospagesizeiramcache-unifiedcache-levelarm,tag-latencyarm,data-latencyprefetch-dataprefetch-instrarm,shared-overridearm,double-linefillarm,double-linefill-incrarm,double-linefill-wraparm,prefetch-droparm,prefetch-offsetbroken-cdbus-widthcap-mmc-highspeedcap-sd-highspeedcd-gpiosvmmc-supplyvqmmc-supplyreg-namescdns,fifo-depthcdns,fifo-widthcdns,trigger-addressspi-max-frequencym25p,fast-readcdns,page-sizecdns,block-sizecdns,read-delaycdns,tshsl-nscdns,tsd2d-nscdns,tchsh-nscdns,tslch-ns#reset-cellsaltr,modrst-offsetaltr,sdr-sysconnum-cscpu1-start-addrreg-shiftreg-io-widthdmasdma-names#phy-cellsphysphy-namesbootargsstdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltlabel