Š žķJ°HEĢ(äE„Aries/DENX MCV EVK/!denx,mcvevkaltr,socfpga-cyclone5altr,socfpgaaliases,/soc/serial0@ffc020004/soc/serial1@ffc03000L[oƒœµĒœl3regs@0xff800000!altr,l3regssyscon‡’€dwmmc0@ff704000!altr,socfpga-dw-mshc‡’p@ µ‹ )-biuciu6:okayŪåļnand@ff900000!altr,socfpga-denali-nand‡’’ønand_datadenali_reg µ  ./nandnand_xecc$ :disabledsram@ffff0000 !mmio-sram‡’’œ,spi@ff705000!!intel,socfpga-qspicdns,qspi-nor‡’pP’  µ—€,< 0% :disabledrstmgr@ffd05000Q !altr,rst-mgr‡’ŠP^œsnoop-control-unit@fffec000!arm,cortex-a9-scu‡’žĄsdr@ffc25000!altr,sdr-ctlsyscon‡’ĀP=œ1sdramedac!altr,sdram-edacq1 µ'spi@fff00000!snps,dw-apb-ssi‡’š µš 22%spi :disabledspi@fff01000!snps,dw-apb-ssi‡’š µ› 23%spi :disabledsysmgr@ffd08000!altr,sys-mgrsyscon‡’Š€@ˆ’Š€Äœ%timer@fffec600!arm,cortex-a9-twd-timer‡’žĘ µ  3timer0@ffc08000!snps,dw-apb-timer µ§‡’Ą€ *timer*%timertimer1@ffc09000!snps,dw-apb-timer µØ‡’Ą *timer+%timertimer2@ffd00000!snps,dw-apb-timer µ©‡’Š timer(%timertimer3@ffd01000!snps,dw-apb-timer µŖ‡’Š timer)%timerserial0@ffc02000!snps,dw-apb-uart‡’Ą  µ¢˜¢ *Æ44“txrx0:okayserial1@ffc03000!snps,dw-apb-uart‡’Ą0 µ£˜¢ *Æ44“txrx1usbphy¾!usb-nop-xceiv:okayœ6usb@ffb00000 !snps,dwc2‡’°’’ µ} 5otg"%dwc2É6 Īusb2-phy :disabledusb@ffb40000 !snps,dwc2‡’“’’ µ€ 5otg#%dwc2É6 Īusb2-phy:okaywatchdog@ffd02000 !snps,dw-wdt‡’Š  µ« &:okaywatchdog@ffd03000 !snps,dw-wdt‡’Š0 µ¬ ' :disabledmemory@0{memory‡@chosenŲserial0:115200n8 #address-cells#size-cellsmodelcompatibleserial0serial1timer0timer1timer2timer3ethernet0stmpe-i2c0enable-methoddevice_typeregnext-level-cachephandleinterrupt-parentinterruptsinterrupt-affinity#interrupt-cellsinterrupt-controllerranges#dma-cellsclocksclock-namesresetsreset-namesfpga-mgrstatus#clock-cellsclock-frequencydiv-regfixed-dividerclk-gateclk-phasesnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blenaltr,sysmgr-sysconinterrupt-namesmac-addresssnps,multicast-filter-binssnps,perfect-filter-entriestx-fifo-depthrx-fifo-depthsnps,axi-configphy-modegpio-controller#gpio-cellssnps,nr-gpiosidblocksirq-gpiots,sample-timets,mod-12bts,ref-selts,adc-freqts,ave-ctrlts,touch-det-delayts,settlingts,fraction-zts,i-driveiramcache-unifiedcache-levelarm,tag-latencyarm,data-latencyprefetch-dataprefetch-instrarm,shared-overridearm,double-linefillarm,double-linefill-incrarm,double-linefill-wraparm,prefetch-droparm,prefetch-offsetbroken-cdbus-widthcap-mmc-highspeedcap-sd-highspeedreg-namescdns,fifo-depthcdns,fifo-widthcdns,trigger-address#reset-cellsaltr,modrst-offsetaltr,sdr-sysconnum-cscpu1-start-addrreg-shiftreg-io-widthdmasdma-names#phy-cellsphysphy-namesstdout-path