8( google,veyron-mighty-rev5google,veyron-mighty-rev4google,veyron-mighty-rev3google,veyron-mighty-rev2google,veyron-mighty-rev1google,veyron-mightygoogle,veyronrockchip,rk3288&7Google Mightyaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/spi@ff110000/ec@0/i2c-tunnelarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12 -@;Br\ hcpu@501cpuarm,cortex-a12 -@;Brhcpu@502cpuarm,cortex-a12 -@;Brhcpu@503cpuarm,cortex-a12 -@;Brhopp-table-0operating-points-v2phopp-126000000{ opp-216000000{  opp-408000000{Q opp-600000000{#F opp-696000000{)|~opp-816000000{0,B@opp-1008000000{<opp-1200000000{Gopp-1416000000{TfrOopp-1512000000{ZJopp-1608000000{_" opp-1704000000{epopp-1800000000{kI\reserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mh timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H ;a  pclktimerdisplay-subsystemrockchip,display-subsystem mmc@ff0c0000rockchip,rk3288-dw-mshcр ;Drvbiuciuciu-driveciu-sample"  @-reset9okay@J\m  Zdefault  mmc@ff0d0000rockchip,rk3288-dw-mshcр ;Eswbiuciuciu-driveciu-sample" ! @-reset9okay@\"8Cdefault btmrvl@2marvell,sd8897-bt&Q defaultmmc@ff0e0000rockchip,rk3288-dw-mshcр ;Ftxbiuciuciu-driveciu-sample" "@-reset 9disabledmmc@ff0f0000rockchip,rk3288-dw-mshcр ;Guybiuciuciu-driveciu-sample" #@-reset9okay@Jdo8Cdefault  !saradc@ff100000rockchip,saradc $~;I[saradcapb_pclkW -saradc-apb 9disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi;ARspiclkapb_pclk" " txrx ,default#$%&9okayec@0google,cros-ec-spi& default'-i2c-tunnelgoogle,cros-ec-i2c-tunnelsbs-battery@bsbs,sbs-battery keyboard-controllergoogle,cros-ec-keyb  ,DF;<=>?@A B CD}0Y1 d"#(  \V |})   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ispi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi;BSspiclkapb_pclk" "txrx -default()*+ 9disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi;CTspiclkapb_pclk""txrx .default,-./9okayS flash@0jedec,spi-nori2c@ff140000rockchip,rk3288-i2c >i2c;Mdefault09okayf2~dtpm@20infineon,slb9645tt i2c@ff150000rockchip,rk3288-i2c ?i2c;Odefault1 9disabledi2c@ff160000rockchip,rk3288-i2c @i2c;Pdefault29okayf2~,ts3a227e@3b ti,ts3a227e;&3default4htrackpad@15elan,ekth3000& default56i2c@ff170000rockchip,rk3288-i2c Ai2c;Qdefault7 9disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7;MUbaudclkapb_pclk""txrxdefault 89:9okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8;NVbaudclkapb_pclk""txrxdefault;9okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9;OWbaudclkapb_pclkdefault<9okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :;PXbaudclkapb_pclk""txrxdefault= 9disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;;QYbaudclkapb_pclk" " txrxdefault> 9disableddma-controller@ff250000arm,pl330arm,primecell%@; apb_pclkh"thermal-zonesreserve-thermal%;I?cpu-thermal%d;I?tripscpu_alert0Ypepassiveh@cpu_alert1Y$epassivehAcpu_critYe criticalcooling-mapsmap0p@0umap1pA0ugpu-thermal%d;I?tripsgpu_alert0Y4epassivehBgpu_critYe criticalcooling-mapsmap0pB uCtsadc@ff280000rockchip,rk3288-tsadc( %;HZtsadcapb_pclk -tsadc-apbinitdefaultsleepDEDFH9okayh?ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irqF8;fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB -stmmaceth 9disabledusb@ff500000 generic-ehciP ;Gusb9okay#usb@ff520000 generic-ohciR );Gusb 9disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T ;otg9hostH usb2-phyA9okayXusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X ;otg9hosto@@ I usb2-phy9okayzIXusb@ff5c0000 generic-ehci\ ; 9disableddma-controller@ff600000arm,pl330arm,primecell`@; apb_pclk 9disabledi2c@ff650000rockchip,rk3288-i2ce <i2c;LdefaultJ9okayf2~dpmic@1brockchip,rk808xin32kwifibt_32kin&3default KLM N#/;H6UbNnN{ hregulatorsDCDC_REG1vdd_arm q qh regulator-state-memDCDC_REG2vdd_gpu 5qhregulator-state-memDCDC_REG3 vcc135_ddrregulator-state-memDCDC_REG4vcc_18w@w@hregulator-state-mem0w@LDO_REG1 vcc33_io2Z2Zh6regulator-state-mem02ZLDO_REG3vdd_10B@B@regulator-state-mem0B@LDO_REG7vdd10_lcd_pwren_h&%&%regulator-state-memSWITCH_REG1 vcc33_lcdhdregulator-state-memLDO_REG6 vcc18_codecw@w@heregulator-state-memLDO_REG4 vccio_sdw@2Zhregulator-state-memLDO_REG5 vcc33_sd2Z2Zhregulator-state-memLDO_REG8 vcc33_ccd2Z2Zregulator-state-memLDO_REG2mic_vccw@w@regulator-state-memi2c@ff660000rockchip,rk3288-i2cf =i2c;NdefaultO9okayf2~ max98090@10maxim,max98090&Pmclk;qdefaultQhpwm@ff680000rockchip,rk3288-pwmhLdefaultR;_9okayhpwm@ff680010rockchip,rk3288-pwmhLdefaultS;_9okayhpwm@ff680020rockchip,rk3288-pwmh LdefaultT;_ 9disabledpwm@ff680030rockchip,rk3288-pwmh0LdefaultU;_ 9disabledsram@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdshpower-controller!rockchip,rk3288-power-controllerWh hipower-domain@9 ;chgfdehilkj$kVWXYZ[\]^Wpower-domain@11 ;opk_`Wpower-domain@12 ;kaWpower-domain@13 ;kbcWreboot-modesyscon-reboot-moderyRBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv; xin24mFHjk$#gׄeрxhрxhhsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwhFedp-phyrockchip,rk3288-dp-phy;h24m9okayhyio-domains"rockchip,rk3288-io-voltage-domain9okay66 6 d ) 5e Busbphyrockchip,rk3288-usb-phy9okayusb-phy@320 ;]phyclk -phy-resethIusb-phy@3344;^phyclk -phy-resethGusb-phy@348H;_phyclk -phy-resethHwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt;p O9okaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif P;T mclkhclkftx 6defaultgF 9disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s P 5;Ri2s_clki2s_hclkfftxrxdefaulth a |9okayhcrypto@ff8a0000rockchip,rk3288-crypto@ 0 ;}aclkhclksclkapb_pclk -crypto-rstiommu@ff900800rockchip,iommu@ ; aclkiface  9disablediommu@ff914000rockchip,iommu @P ; aclkiface   9disabledrga@ff920000rockchip,rk3288-rga ;jaclkhclksclk i ilm -coreaxiahbvop@ff930000rockchip,rk3288-vop  ;aclk_vopdclk_vophclk_vop i def -axiahbdclk j9okayporth endpoint@0 khendpoint@1 lh{endpoint@2 mhtendpoint@3 nhwiommu@ff930300rockchip,iommu ; aclkiface i  9okayhjvop@ff940000rockchip,rk3288-vop  ;aclk_vopdclk_vophclk_vop i  -axiahbdclk o9okayporth endpoint@0 phendpoint@1 qh|endpoint@2 rhuendpoint@3 shxiommu@ff940300rockchip,iommu ; aclkiface i  9okayhomipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ ;~d refpclk i F 9disabledportsportendpoint@0 thmendpoint@1 uhrlvds@ff96c000rockchip,rk3288-lvds@;g pclk_lvdslcdcv i F 9disabledportsport@0endpoint@0 whnendpoint@1 xhsdp@ff970000rockchip,rk3288-dp@ b;icdppclkydp i o-dpF9okaydefaultzportsport@0endpoint@0 {hlendpoint@1 |hqport@1endpoint@0 }hhdmi@ff980000rockchip,rk3288-dw-hdmi PF g;hmniahbisfrcec i 9okaydefaultunwedge~hportsportendpoint@0 hkendpoint@1 hpvideo-codec@ff9a0000rockchip,rk3288-vpu   vepuvdpu; aclkhclk  i iommu@ff9a0800rockchip,iommu ; aclkiface  i hiommu@ff9c0440rockchip,iommu @@@ o; aclkiface  9disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ jobmmugpu;  i 9okay hCopp-table-1operating-points-v2hopp-100000000{~opp-200000000{ ~opp-300000000{B@opp-400000000{ׄopp-600000000{#Fqos@ffaa0000rockchip,rk3288-qossyscon hbqos@ffaa0080rockchip,rk3288-qossyscon hcqos@ffad0000rockchip,rk3288-qossyscon hWqos@ffad0100rockchip,rk3288-qossyscon hXqos@ffad0180rockchip,rk3288-qossyscon hYqos@ffad0400rockchip,rk3288-qossyscon hZqos@ffad0480rockchip,rk3288-qossyscon h[qos@ffad0500rockchip,rk3288-qossyscon hVqos@ffad0800rockchip,rk3288-qossyscon h\qos@ffad0880rockchip,rk3288-qossyscon h]qos@ffad0900rockchip,rk3288-qossyscon h^qos@ffae0000rockchip,rk3288-qossyscon haqos@ffaf0000rockchip,rk3288-qossyscon h_qos@ffaf0080rockchip,rk3288-qossyscon h`dma-controller@ffb20000arm,pl330arm,primecell@; apb_pclkhfefuse@ffb40000rockchip,rk3288-efuse ;q pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400  @ @ `   hpinctrlrockchip,rk3288-pinctrlFdefaultsleepgpio@ff750000rockchip,gpio-banku Q;@  %   1PMIC_SLEEP_APDDRIO_PWROFFDDRIO_RETENTS3A227E_INT_LPMIC_INT_LPWR_KEY_LAP_LID_INT_LEC_IN_RWAC_PRESENT_APRECOVERY_SW_LOTP_OUTHOST1_PWR_ENUSBOTG_PWREN_HAP_WARM_RESET_HnFALUT2I2C0_SDA_PMICI2C0_SCL_PMICSUSPEND_LUSB_INTh3gpio@ff780000rockchip,gpio-bankx R;A  %  gpio@ff790000rockchip,gpio-banky S;B  %  M 1CONFIG0CONFIG1CONFIG2CONFIG3EMMC_RST_LBL_PWR_ENAVDD_1V8_DISP_ENhgpio@ff7a0000rockchip,gpio-bankz T;C  %   1FLASH0_D0FLASH0_D1FLASH0_D2FLASH0_D3FLASH0_D4FLASH0_D5FLASH0_D6FLASH0_D7FLASH0_CS2/EMMC_CMDFLASH0_DQS/EMMC_CLKOgpio@ff7b0000rockchip,gpio-bank{ U;D  %   1UART0_RXDUART0_TXDUART0_CTSUART0_RTSSDIO0_D0SDIO0_D1SDIO0_D2SDIO0_D3SDIO0_CMDSDIO0_CLKBT_DEV_WAKEWIFI_ENABLE_HBT_ENABLE_LWIFI_HOST_WAKEBT_HOST_WAKEhgpio@ff7c0000rockchip,gpio-bank| V;E  %  A 1SPI0_CLKSPI0_CS0SPI0_TXDSPI0_RXDVCC50_HDMI_ENhgpio@ff7d0000rockchip,gpio-bank} W;F  %   1I2S0_SCLKI2S0_LRCK_RXI2S0_LRCK_TXI2S0_SDII2S0_SDO0HP_DET_HALS_INTINT_CODECI2S0_CLKI2C2_SDAI2C2_SCLMICDETSDMMC_D0SDMMC_D1SDMMC_D2SDMMC_D3SDMMC_CLKSDMMC_CMDhPgpio@ff7e0000rockchip,gpio-bank~ X;G  %   1LCDC_BLPWM_LOGBL_ENTRACKPAD_INTTPM_INT_HSDMMC_DET_LAP_FLASH_WP_LEC_INTCPU_NMIDVSOKSDMMC_WPEDP_HPDDVS1nFALUT1LCD_ENDVS2VCC5V_GOOD_HI2C4_SDA_TPI2C4_SCL_TPI2C5_SDA_HDMII2C5_SCL_HDMI5V_DRVUART2_RXDUART2_TXDh gpio@ff7f0000rockchip,gpio-bank Y;H  %  ^ 1RAM_ID0RAM_ID1RAM_ID2RAM_ID3I2C1_SDA_TPMI2C1_SCL_TPMSPI2_CLKSPI2_CS0SPI2_RXDSPI2_TXDhdmihdmi-cec-c0 Ahdmi-cec-c7 Ahdmi-ddc Ah~hdmi-ddc-unwedge Ahvcc50-hdmi-en Ahpcfg-output-low Ohpcfg-pull-up Zhpcfg-pull-down ghpcfg-pull-none vhpcfg-pull-none-12ma v hsuspendglobal-pwroff Ahddrio-pwroff Ahddr0-retention Ahddr1-retention Asuspend-l-wake Ahsuspend-l-sleep Ahedpedp-hpd A hzi2c0i2c0-xfer AhJi2c1i2c1-xfer Ah0i2c2i2c2-xfer A  hOi2c3i2c3-xfer Ah1i2c4i2c4-xfer Ah2i2c5i2c5-xfer Ah7i2s0i2s0-bus` Ahhlcdclcdc-ctl@ Ahvsdmmcsdmmc-clk Ahsdmmc-cmd Ahsdmmc-cd Asdmmc-bus1 Asdmmc-bus4@ Ahsdmmc-cd-disabled Ahsdmmc-cd-pin Ahsdmmc-wp-pin A hsdio0sdio0-bus1 Asdio0-bus4@ Ahsdio0-cmd Ahsdio0-clk Ahsdio0-cd Asdio0-wp Asdio0-pwr Asdio0-bkpwr Asdio0-int Awifienable-h Ahbt-enable-l Abt-host-wake Abt-host-wake-l Ahbt-dev-wake-sleep Ahbt-dev-wake-awake Ahbt-dev-wake Asdio1sdio1-bus1 Asdio1-bus4@ Asdio1-cd Asdio1-wp Asdio1-bkpwr Asdio1-int Asdio1-cmd Asdio1-clk Asdio1-pwr A emmcemmc-clk Ahemmc-cmd Ah emmc-pwr A emmc-bus1 Aemmc-bus4@ Aemmc-bus8 Ah!emmc-reset A hspi0spi0-clk A h#spi0-cs0 A h&spi0-tx Ah$spi0-rx Ah%spi0-cs1 Aspi1spi1-clk A h(spi1-cs0 A h+spi1-rx Ah*spi1-tx Ah)spi2spi2-cs1 Aspi2-clk Ah,spi2-cs0 Ah/spi2-rx Ah.spi2-tx A h-uart0uart0-xfer Ah8uart0-cts Ah9uart0-rts Ah:uart1uart1-xfer A h;uart1-cts A uart1-rts A uart2uart2-xfer Ah<uart3uart3-xfer Ah=uart3-cts A uart3-rts A uart4uart4-xfer Ah>uart4-cts A uart4-rts A tsadcotp-pin A hDotp-out A hEpwm0pwm0-pin AhRpwm1pwm1-pin AhSpwm2pwm2-pin AhTpwm3pwm3-pin AhUgmacrgmii-pins A rmii-pins Aspdifspdif-tx A hgpcfg-pull-none-drv-8ma v hpcfg-pull-up-drv-8ma Z pcfg-output-high hbuttonspwr-key-l Ahap-lid-int-l Ahpmicpmic-int-l AhKdvs-1 A hLdvs-2 AhMrebootap-warm-reset-h A hrecovery-switchrec-mode-l A tpmtpm-int-h Awrite-protectfw-wp-ap Acodechp-det Ahint-codec AhQmic-det A hheadsetts3a227e-int-l Ah4backlightbl_pwr_en A hbl-en Ahlcdlcd-en Ahavdd-1v8-disp-en A hchargerac-present-ap Ahcros-ecec-int Ah'trackpadtrackpad-int Ah5usb-hosthost1-pwr-en A husbotg-pwren-h A hbuck-5vdrv-5v Ahchosen serial2:115200n8memorymemorypower-button gpio-keysdefaultkey-power Power 3 t dgpio-restart gpio-restart 3 default emmc-pwrseqmmc-pwrseq-emmcdefault hsdio-pwrseqmmc-pwrseq-simple; ext_clockdefault hvcc-5vregulator-fixedvcc_5vLK@LK@   defaulthNvcc33-sysregulator-fixed vcc33_sys2Z2Z hvcc50-hdmiregulator-fixed vcc50_hdmi N  defaultvdd-logicpwm-regulator vdd_logic   { )~psound!rockchip,rockchip-audio-max98090default