p8( P%asus,rk3288-tinker-srockchip,rk3288&$7Rockchip RK3288 Asus Tinker Board Saliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'@5<rV bcpu@501cpuarm,cortex-a12'@5<rbcpu@502cpuarm,cortex-a12'@5<rbcpu@503cpuarm,cortex-a12'@5<rbopp-table-0operating-points-v2jbopp-126000000u| opp-216000000u | opp-312000000u| opp-408000000uQ| opp-600000000u#F| opp-696000000u)||~opp-816000000u0,|B@opp-1008000000u<|opp-1200000000uG|opp-1416000000uTfr|Oopp-1512000000uZJ| opp-1608000000u_"|popp-1704000000ue|popp-1800000000ukI|\reserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mb timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 5a  pclktimerdisplay-subsystemrockchip,display-subsystem mmc@ff0c0000rockchip,rk3288-dw-mshcр 5Drvbiuciuciu-driveciu-sample  @'reset3okay:DVgq|default mmc@ff0d0000rockchip,rk3288-dw-mshc 5Eswbiuciuciu-driveciu-sample ! @'reset3okay:V|defaultmmc@ff0e0000rockchip,rk3288-dw-mshcр 5Ftxbiuciuciu-driveciu-sample "@'reset 3disabledmmc@ff0f0000rockchip,rk3288-dw-mshcр 5Guybiuciuciu-driveciu-sample #@'reset3okay:D|defaultsaradc@ff100000rockchip,saradc $,5I[saradcapb_pclkW 'saradc-apb3okay>spi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARspiclkapb_pclkJ  Otxrx ,|default !"# 3disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSspiclkapb_pclkJ Otxrx -|default$%&' 3disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTspiclkapb_pclkJOtxrx .|default()*+ 3disabledi2c@ff140000rockchip,rk3288-i2c >i2c5M|default, 3disabledi2c@ff150000rockchip,rk3288-i2c ?i2c5O|default- 3disabledi2c@ff160000rockchip,rk3288-i2c @i2c5P|default. 3disabledi2c@ff170000rockchip,rk3288-i2c Ai2c5Q|default/3okaybtserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7Yc5MUbaudclkapb_pclkJOtxrx|default03okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8Yc5NVbaudclkapb_pclkJOtxrx|default13okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9Yc5OWbaudclkapb_pclk|default23okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :Yc5PXbaudclkapb_pclkJOtxrx|default33okayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;Yc5QYbaudclkapb_pclkJ  Otxrx|default43okaydma-controller@ff250000arm,pl330arm,primecell%@p{5 apb_pclkbthermal-zonesreserve-thermal5cpu-thermald5tripscpu_alert0ppassiveb6cpu_alert1$passiveb7cpu_crit_ criticalcooling-mapsmap060map170gpu-thermald5tripsgpu_alert0ppassiveb8gpu_crit_ criticalcooling-mapsmap08 9tsadc@ff280000rockchip,rk3288-tsadc( %5HZtsadcapb_pclk 'tsadc-apb|initdefaultsleep: ;: 6<Cs3okayZqb5ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irq6<85fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB 'stmmaceth3okay=inputrgmii>|default? @  'B@0(usb@ff500000 generic-ehciP 51A6usb3okayusb@ff520000 generic-ohciR )51A6usb 3disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 5otg@host1B 6usb2-phyH3okayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 5otg@otg_q@@ 1C 6usb2-phy3okayusb@ff5c0000 generic-ehci\ 5 3disableddma-controller@ff600000arm,pl330arm,primecell`@p{5 apb_pclk 3disabledi2c@ff650000rockchip,rk3288-i2ce <i2c5L|defaultD3okaypmic@1brockchip,rk808&Exin32krk808-clkout2E E |defaultFGHIJJJJJJ(5JBObregulatorsDCDC_REG1\p q\vdd_armpb regulator-state-memDCDC_REG2\p Pvdd_gpupbzregulator-state-memB@DCDC_REG3\pvcc_ddrregulator-state-memDCDC_REG4\p2Z2Zvcc_iobregulator-state-mem2ZLDO_REG1\pw@w@ vcc18_ldo1bregulator-state-memw@LDO_REG2\p2Z2Z vcc33_mipiregulator-state-memLDO_REG3\pB@B@vdd_10regulator-state-memB@LDO_REG4\pw@w@ vcc18_codecregulator-state-memw@LDO_REG5\pw@2Z vccio_sdbregulator-state-mem2ZLDO_REG6\pB@B@ vdd10_lcdregulator-state-memB@LDO_REG7\pw@w@vcc_18bregulator-state-memw@LDO_REG8\pw@w@ vcc18_lcdregulator-state-memw@SWITCH_REG1\p vcc33_sdbregulator-state-memSWITCH_REG2\p vcc33_lanb>regulator-state-memi2c@ff660000rockchip,rk3288-i2cf =i2c5N|defaultK3okaypwm@ff680000rockchip,rk3288-pwmh#|defaultL5_3okaypwm@ff680010rockchip,rk3288-pwmh#|defaultM5_ 3disabledpwm@ff680020rockchip,rk3288-pwmh #|defaultN5_ 3disabledpwm@ff680030rockchip,rk3288-pwmh0#|defaultO5_ 3disabledsram@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsbpower-controller!rockchip,rk3288-power-controller.h bapower-domain@9 5chgfdehilkj$BPQRSTUVWX.power-domain@11 5opBYZ.power-domain@12 5B[.power-domain@13 5B\].reboot-modesyscon-reboot-modeIPRB\RBjRB zRBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv5 xin24m6<Hjk$#gׄeрxhрxhbsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwb<edp-phyrockchip,rk3288-dp-phy5h24m 3disabledbqio-domains"rockchip,rk3288-io-voltage-domain3okayusbphyrockchip,rk3288-usb-phy3okayusb-phy@320 5]phyclk 'phy-resetbCusb-phy@33445^phyclk 'phy-resetbAusb-phy@348H5_phyclk 'phy-resetbBwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt5p O3okaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif5T mclkhclkJ^Otx 6|default_6< 3disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 55Ri2s_clki2s_hclkJ^^Otxrx|default`3okaybcrypto@ff8a0000rockchip,rk3288-crypto@ 0 5}aclkhclksclkapb_pclk 'crypto-rstiommu@ff900800rockchip,iommu@ 5 aclkiface 3disablediommu@ff914000rockchip,iommu @P 5 aclkiface  3disabledrga@ff920000rockchip,rk3288-rga 5jaclkhclksclk;a ilm 'coreaxiahbvop@ff930000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vop;a def 'axiahbdclkIb3okayportb endpoint@0Pcbvendpoint@1Pdbrendpoint@2Peblendpoint@3Pfboiommu@ff930300rockchip,iommu 5 aclkiface;a 3okaybbvop@ff940000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vop;a  'axiahbdclkIg3okayportb endpoint@0Phbwendpoint@1Pibsendpoint@2Pjbmendpoint@3Pkbpiommu@ff940300rockchip,iommu 5 aclkiface;a 3okaybgmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 5~d refpclk;a 6< 3disabledportsportendpoint@0Plbeendpoint@1Pmbjlvds@ff96c000rockchip,rk3288-lvds@5g pclk_lvds|lcdcn;a 6< 3disabledportsport@0endpoint@0Pobfendpoint@1Ppbkdp@ff970000rockchip,rk3288-dp@ b5icdppclk1q6dp;a o'dp6< 3disabledportsport@0endpoint@0Prbdendpoint@1Psbihdmi@ff980000rockchip,rk3288-dw-hdmic6< g5hmniahbisfrcec;a 3okay`t|defaultubportsportendpoint@0Pvbcendpoint@1Pwbhvideo-codec@ff9a0000rockchip,rk3288-vpu   vepuvdpu5 aclkhclkIx;a iommu@ff9a0800rockchip,iommu 5 aclkiface;a bxiommu@ff9c0440rockchip,iommu @@@ o5 aclkiface 3disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ jobmmugpu5y;a 3okaylzb9opp-table-1operating-points-v2byopp-100000000u|~opp-200000000u |~opp-300000000u|B@opp-400000000uׄ|opp-600000000u#F|qos@ffaa0000rockchip,rk3288-qossyscon b\qos@ffaa0080rockchip,rk3288-qossyscon b]qos@ffad0000rockchip,rk3288-qossyscon bQqos@ffad0100rockchip,rk3288-qossyscon bRqos@ffad0180rockchip,rk3288-qossyscon bSqos@ffad0400rockchip,rk3288-qossyscon bTqos@ffad0480rockchip,rk3288-qossyscon bUqos@ffad0500rockchip,rk3288-qossyscon bPqos@ffad0800rockchip,rk3288-qossyscon bVqos@ffad0880rockchip,rk3288-qossyscon bWqos@ffad0900rockchip,rk3288-qossyscon bXqos@ffae0000rockchip,rk3288-qossyscon b[qos@ffaf0000rockchip,rk3288-qossyscon bYqos@ffaf0080rockchip,rk3288-qossyscon bZdma-controller@ffb20000arm,pl330arm,primecell@p{5 apb_pclkb^efuse@ffb40000rockchip,rk3288-efuse 5q pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400x@ @ `   bpinctrlrockchip,rk3288-pinctrl6<gpio@ff750000rockchip,gpio-banku Q5@xbEgpio@ff780000rockchip,gpio-bankx R5Axbgpio@ff790000rockchip,gpio-banky S5Bxgpio@ff7a0000rockchip,gpio-bankz T5Cxgpio@ff7b0000rockchip,gpio-bank{ U5Dxb@gpio@ff7c0000rockchip,gpio-bank| V5Exgpio@ff7d0000rockchip,gpio-bank} W5Fxgpio@ff7e0000rockchip,gpio-bank~ X5Gxbgpio@ff7f0000rockchip,gpio-bank Y5Hxhdmihdmi-cec-c0{buhdmi-cec-c7{hdmi-ddc {{hdmi-ddc-unwedge |{pcfg-output-lowb|pcfg-pull-upb}pcfg-pull-downb~pcfg-pull-noneb{pcfg-pull-none-12ma bsuspendglobal-pwroff{bGddrio-pwroff{ddr0-retention}ddr1-retention}edpedp-hpd ~i2c0i2c0-xfer {{bDi2c1i2c1-xfer {{b,i2c2i2c2-xfer  { {bKi2c3i2c3-xfer {{b-i2c4i2c4-xfer {{b.i2c5i2c5-xfer {{b/i2s0i2s0-bus`{{{{{{b`lcdclcdc-ctl@{{{{bnsdmmcsdmmc-clkb sdmmc-cmdbsdmmc-cd}bsdmmc-bus1}sdmmc-bus4@bsdmmc-pwr {bsdio0sdio0-bus1}sdio0-bus4@}}}}bsdio0-cmd}bsdio0-clk{bsdio0-cd}sdio0-wp}sdio0-pwr}sdio0-bkpwr}sdio0-int}bsdio1sdio1-bus1}sdio1-bus4@}}}}sdio1-cd}sdio1-wp}sdio1-bkpwr}sdio1-int}sdio1-cmd}sdio1-clk{sdio1-pwr }emmcemmc-clk{bemmc-cmd}bemmc-pwr }bemmc-bus1}emmc-bus4@}}}}emmc-bus8}}}}}}}}bspi0spi0-clk }b spi0-cs0 }b#spi0-tx}b!spi0-rx}b"spi0-cs1}spi1spi1-clk }b$spi1-cs0 }b'spi1-rx}b&spi1-tx}b%spi2spi2-cs1}spi2-clk}b(spi2-cs0}b+spi2-rx}b*spi2-tx }b)uart0uart0-xfer }{b0uart0-cts}uart0-rts{uart1uart1-xfer } {b1uart1-cts }uart1-rts {uart2uart2-xfer }{b2uart3uart3-xfer }{b3uart3-cts }uart3-rts {uart4uart4-xfer }{b4uart4-cts }uart4-rts {tsadcotp-pin {b:otp-out {b;pwm0pwm0-pin{bLpwm1pwm1-pin{bMpwm2pwm2-pin{bNpwm3pwm3-pin{bOgmacrgmii-pins{{{{{{{ {{b?rmii-pins{{{{{{{{{{spdifspdif-tx {b_pcfg-pull-none-drv-8mabpcfg-pull-up-drv-8mabbacklightbl-en{buttonspwrbtn}beth_phyeth-phy-pwr{pmicpmic-int}bFdvs-1 ~bHdvs-2 ~bIusbhost-vbus-drv{pwr-3g{sdiowifi-enable {{bchosen serial2:115200n8memorymemoryexternal-gmac-clock fixed-clocksY@ ext_gmacb=gpio-keys gpio-keys |defaultbutton E "t -GPIO Key Power 3 Ddgpio-leds gpio-ledsled-0  Vmmc0led-1  Vheartbeatled-2 E Vdefault-onsdio-pwrseqmmc-pwrseq-simple5 ext_clock|default l@@bsoundsimple-audio-card xi2s rockchip,tinker-codec simple-audio-card,codec simple-audio-card,cpu vsys-regulatorregulator-fixedvcc_sysLK@LK@\pbJsdmmc-regulatorregulator-fixed  |defaultvcc_sd2Z2Z   #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedbroken-cddisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplycap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50mmc-hs200-1_8vmmc-ddr-1_8v#io-channel-cellsvref-supplydmasdma-namesreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesassigned-clocksassigned-clock-parentsclock_in_outphy-modephy-supplysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizedvs-gpiosrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvddio-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-nameregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellssdcard-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-busmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthstdout-pathautorepeatlinux,codelabellinux,input-typedebounce-intervallinux,default-triggerreset-gpiossimple-audio-card,formatsimple-audio-card,namesimple-audio-card,mclk-fssound-daistartup-delay-usvin-supply