8( L*rockchip,rk3288-evb-rk808rockchip,rk3288&7Rockchip RK3288 EVB RK808aliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'@5<rV bcpu@501cpuarm,cortex-a12'@5<rbcpu@502cpuarm,cortex-a12'@5<rbcpu@503cpuarm,cortex-a12'@5<rbopp-table-0operating-points-v2jbopp-126000000u| opp-216000000u | opp-312000000u| opp-408000000uQ| opp-600000000u#F| opp-696000000u)||~opp-816000000u0,|B@opp-1008000000u<|opp-1200000000uG|opp-1416000000uTfr|Oopp-1512000000uZJ| opp-1608000000u_"|preserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mb timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 5a  pclktimerdisplay-subsystemrockchip,display-subsystem mmc@ff0c0000rockchip,rk3288-dw-mshcр 5Drvbiuciuciu-driveciu-sample  @'reset3okay:DVgydefault mmc@ff0d0000rockchip,rk3288-dw-mshcр 5Eswbiuciuciu-driveciu-sample ! @'reset 3disabledmmc@ff0e0000rockchip,rk3288-dw-mshcр 5Ftxbiuciuciu-driveciu-sample "@'reset 3disabledmmc@ff0f0000rockchip,rk3288-dw-mshcр 5Guybiuciuciu-driveciu-sample #@'reset3okay:Dydefaultsaradc@ff100000rockchip,saradc $5I[saradcapb_pclkW 'saradc-apb3okayb{spi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARspiclkapb_pclk  txrx ,default 3disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSspiclkapb_pclk txrx -default  3disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTspiclkapb_pclktxrx .default!"#$ 3disabledi2c@ff140000rockchip,rk3288-i2c >i2c5Mdefault% 3disabledi2c@ff150000rockchip,rk3288-i2c ?i2c5Odefault& 3disabledi2c@ff160000rockchip,rk3288-i2c @i2c5Pdefault' 3disabledi2c@ff170000rockchip,rk3288-i2c Ai2c5Qdefault(3okaybnserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 75MUbaudclkapb_pclktxrxdefault)3okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 85NVbaudclkapb_pclktxrxdefault*3okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 95OWbaudclkapb_pclkdefault+3okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :5PXbaudclkapb_pclktxrxdefault,3okayserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;5QYbaudclkapb_pclk  txrxdefault-3okaydma-controller@ff250000arm,pl330arm,primecell%@-5 apb_pclkbthermal-zonesreserve-thermalDZh.cpu-thermalDdZh.tripscpu_alert0xppassiveb/cpu_alert1x$passiveb0cpu_critx_ criticalcooling-mapsmap0/0map100gpu-thermalDdZh.tripsgpu_alert0xppassiveb1gpu_critx_ criticalcooling-mapsmap01 2tsadc@ff280000rockchip,rk3288-tsadc( %5HZtsadcapb_pclk 'tsadc-apbinitdefaultsleep3435s3okayb.ethernet@ff290000rockchip,rk3288-gmac)#macirqeth_wake_irq585fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB 'stmmaceth3okay36>rgmiiGinput T7d z'B@8default90usb@ff500000 generic-ehciP 5:usb3okayusb@ff520000 generic-ohciR )5:usb 3disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 5otghost; usb2-phy3okayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 5otgotg@@ < usb2-phy 3disabledusb@ff5c0000 generic-ehci\ 5 3disableddma-controller@ff600000arm,pl330arm,primecell`@-5 apb_pclk 3disabledi2c@ff650000rockchip,rk3288-i2ce <i2c5Ldefault=3okaypmic@1brockchip,rk808&>default?@&Gxin32krk808-clkout2UAaAmAyAAABBABCregulatorsDCDC_REG1 q'p?vdd_armb regulator-state-memNDCDC_REG2 P'?vdd_gpubsregulator-state-memgB@DCDC_REG3?vcc_ddrregulator-state-memgDCDC_REG42Z'2Z?vcc_iobBregulator-state-memg2ZLDO_REG12Z'2Z ?vccio_pmubCregulator-state-memg2ZLDO_REG22Z'2Z?vcc_tpregulator-state-memNLDO_REG3B@'B@?vdd_10regulator-state-memgB@LDO_REG4w@'w@ ?vcc18_lcdregulator-state-memgw@LDO_REG5w@'2Z ?vccio_sdbregulator-state-memg2ZLDO_REG6B@'B@ ?vdd10_lcdregulator-state-memgB@LDO_REG7w@'w@?vcc_18bregulator-state-memgw@LDO_REG82Z'2Z ?vcca_codecregulator-state-memg2ZSWITCH_REG1?vcc_wlregulator-state-memgSWITCH_REG2?vcc_lcdbregulator-state-memgi2c@ff660000rockchip,rk3288-i2cf =i2c5NdefaultD 3disabledpwm@ff680000rockchip,rk3288-pwmhdefaultE5_3okayb~pwm@ff680010rockchip,rk3288-pwmhdefaultF5_ 3disabledpwm@ff680020rockchip,rk3288-pwmh defaultG5_ 3disabledpwm@ff680030rockchip,rk3288-pwmh0defaultH5_ 3disabledsram@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsbpower-controller!rockchip,rk3288-power-controllerh bZpower-domain@9 5chgfdehilkj$IJKLMNOPQpower-domain@11 5opRSpower-domain@12 5Tpower-domain@13 5UVreboot-modesyscon-reboot-modeRBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv5 xin24m5Hjk$ #gׄeрxhрxhbsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwb5edp-phyrockchip,rk3288-dp-phy5h24m 3okaybjio-domains"rockchip,rk3288-io-voltage-domain 3disabledusbphyrockchip,rk3288-usb-phy3okayusb-phy@320  5]phyclk 'phy-resetb<usb-phy@334 45^phyclk 'phy-resetb:usb-phy@348 H5_phyclk 'phy-resetb;watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt5p O3okaysound@ff8b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif+5T mclkhclkWtx 6defaultX5 3disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s+ 55Ri2s_clki2s_hclkWWtxrxdefaultY<W 3disabledcrypto@ff8a0000rockchip,rk3288-crypto@ 0 5}aclkhclksclkapb_pclk 'crypto-rstiommu@ff900800rockchip,iommu@ 5 aclkifaceq 3disablediommu@ff914000rockchip,iommu @P 5 aclkifaceq~ 3disabledrga@ff920000rockchip,rk3288-rga 5jaclkhclksclkZ ilm 'coreaxiahbvop@ff930000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vopZ def 'axiahbdclk[3okayportb endpoint@0\boendpoint@1]bkendpoint@2^beendpoint@3_bhiommu@ff930300rockchip,iommu 5 aclkifaceZ q3okayb[vop@ff940000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vopZ  'axiahbdclk`3okayportb endpoint@0abpendpoint@1bblendpoint@2cbfendpoint@3dbiiommu@ff940300rockchip,iommu 5 aclkifaceZ q3okayb`mipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 5~d refpclkZ 5 3disabledportsportendpoint@0eb^endpoint@1fbclvds@ff96c000rockchip,rk3288-lvds@5g pclk_lvdslcdcgZ 5 3disabledportsport@0endpoint@0hb_endpoint@1ibddp@ff970000rockchip,rk3288-dp@ b5icdppclkjdpZ o'dp53okayportsport@0endpoint@0kb]endpoint@1lbbport@1endpoint@0mbhdmi@ff980000rockchip,rk3288-dw-hdmi+5 g5hmniahbisfrcecZ 3okaynportsportendpoint@0ob\endpoint@1pbavideo-codec@ff9a0000rockchip,rk3288-vpu   #vepuvdpu5 aclkhclkqZ iommu@ff9a0800rockchip,iommu 5 aclkifaceqZ bqiommu@ff9c0440rockchip,iommu @@@ o5 aclkifaceq 3disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ #jobmmugpu5rZ 3okaysb2opp-table-1operating-points-v2bropp-100000000u|~opp-200000000u |~opp-300000000u|B@opp-400000000uׄ|opp-600000000u#F|qos@ffaa0000rockchip,rk3288-qossyscon bUqos@ffaa0080rockchip,rk3288-qossyscon bVqos@ffad0000rockchip,rk3288-qossyscon bJqos@ffad0100rockchip,rk3288-qossyscon bKqos@ffad0180rockchip,rk3288-qossyscon bLqos@ffad0400rockchip,rk3288-qossyscon bMqos@ffad0480rockchip,rk3288-qossyscon bNqos@ffad0500rockchip,rk3288-qossyscon bIqos@ffad0800rockchip,rk3288-qossyscon bOqos@ffad0880rockchip,rk3288-qossyscon bPqos@ffad0900rockchip,rk3288-qossyscon bQqos@ffae0000rockchip,rk3288-qossyscon bTqos@ffaf0000rockchip,rk3288-qossyscon bRqos@ffaf0080rockchip,rk3288-qossyscon bSdma-controller@ffb20000arm,pl330arm,primecell@-5 apb_pclkbWefuse@ffb40000rockchip,rk3288-efuse 5q pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400@ @ `   bpinctrlrockchip,rk3288-pinctrl5gpio@ff750000rockchip,gpio-banku Q5@b>gpio@ff780000rockchip,gpio-bankx R5Agpio@ff790000rockchip,gpio-banky S5Bgpio@ff7a0000rockchip,gpio-bankz T5Cgpio@ff7b0000rockchip,gpio-bank{ U5Db7gpio@ff7c0000rockchip,gpio-bank| V5Egpio@ff7d0000rockchip,gpio-bank} W5Fgpio@ff7e0000rockchip,gpio-bank~ X5Gb|gpio@ff7f0000rockchip,gpio-bank Y5Hhdmihdmi-cec-c0"thdmi-cec-c7"thdmi-ddc "tthdmi-ddc-unwedge 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"vtb+uart3uart3-xfer "vtb,uart3-cts" vuart3-rts" tuart4uart4-xfer "vtb-uart4-cts" vuart4-rts" ttsadcotp-pin" tb3otp-out" tb4pwm0pwm0-pin"tbEpwm1pwm1-pin"tbFpwm2pwm2-pin"tbGpwm3pwm3-pin"tbHgmacrgmii-pins"ttttzzzzttt zzttb9rmii-pins"ttttttttttspdifspdif-tx" tbXpcfg-pull-none-drv-8madbxpcfg-pull-up-drv-8ma;dbybacklightbl-en"tb}buttonspwrbtn"vblcdlcd-cs"tbpmicpmic-int"vb?usbhost-vbus-drv"tbeth_phyeth-phy-pwr"tbmemory@0memoryadc-keys adc-keyss{buttonsw@button-up Volume Upsbutton-down Volume Downrbutton-menuMenu button-escEscB@button-homeHomef backlightpwm-backlight  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~ |default} ~B@bexternal-gmac-clock fixed-clocksY@ ext_gmacb8panellg,lp079qx1-sp0v  | portsportendpointbmgpio-keys gpio-keys )defaultkey-power >tGPIO Key Power 4G Edvcc-host-regulatorregulator-fixed W _>default ?vcc_hostvcc-phy-regulatorregulator-fixed W _>default?vcc_phy2Z'2Zb6vsys-regulatorregulator-fixed?vcc_sysLK@'LK@bAsdmmc-regulatorregulator-fixed _| default?vcc_sd2Z'2Z j {Bb #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaydisable-wppinctrl-namespinctrl-0vmmc-supplyvqmmc-supplynon-removable#io-channel-cellsvref-supplydmasdma-namesreg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphy-supplyphy-modeclock_in_outsnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usassigned-clocksassigned-clock-parentstx_delayrx_delayphysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvddio-supplyregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-nameregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cells#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointforce-hpdddc-i2c-busmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthio-channelsio-channel-nameskeyup-threshold-microvoltlabellinux,codepress-threshold-microvoltbrightness-levelsdefault-brightness-levelenable-gpiospwmsbacklightpower-supplyautorepeatlinux,input-typedebounce-intervalenable-active-highstartup-delay-usvin-supply