Ð þíU5HNÐ(eNˆsamtec VIN|ING FPGA1!samtec,viningaltr,socfpga-cyclone5altr,socfpgaaliases,/soc/serial0@ffc020004/soc/serial1@ffc03000Q #address-cells#size-cellsmodelcompatibleserial0serial1timer0timer1timer2timer3ethernet0ethernet1enable-methoddevice_typeregnext-level-cachephandleinterrupt-parentinterruptsinterrupt-affinity#interrupt-cellsinterrupt-controllerranges#dma-cellsclocksclock-namesresetsreset-namesfpga-mgrstatus#clock-cellsclock-frequencydiv-regfixed-dividerclk-gateclk-phasesnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blenaltr,sysmgr-sysconinterrupt-namesmac-addresssnps,multicast-filter-binssnps,perfect-filter-entriestx-fifo-depthrx-fifo-depthsnps,axi-configphy-modephy-handlesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usrxd0-skew-psrxd1-skew-psrxd2-skew-psrxd3-skew-pstxd0-skew-pstxd1-skew-pstxd2-skew-pstxd3-skew-pstxen-skew-pstxc-skew-psrxdv-skew-psrxc-skew-psgpio-controller#gpio-cellssnps,nr-gpiospagesizeiramcache-unifiedcache-levelarm,tag-latencyarm,data-latencyprefetch-dataprefetch-instrarm,shared-overridearm,double-linefillarm,double-linefill-incrarm,double-linefill-wraparm,prefetch-droparm,prefetch-offsetbroken-cdbus-widthcap-mmc-highspeedcap-sd-highspeedreg-namescdns,fifo-depthcdns,fifo-widthcdns,trigger-addressspi-max-frequencym25p,fast-readcdns,page-sizecdns,block-sizecdns,read-delaycdns,tshsl-nscdns,tsd2d-nscdns,tchsh-nscdns,tslch-ns#reset-cellsaltr,modrst-offsetaltr,sdr-sysconnum-cscpu1-start-addrreg-shiftreg-io-widthdmasdma-names#phy-cellsphysphy-namesdr_modebootargsstdout-pathlabellinux,coderegulator-nameregulator-min-microvoltregulator-max-microvoltstartup-delay-usenable-active-highregulator-always-on