g8( _Kgoogle,veyron-brain-rev0google,veyron-braingoogle,veyronrockchip,rk3288& 7Google Brainaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'@5<rV bcpu@501cpuarm,cortex-a12'@5<rbcpu@502cpuarm,cortex-a12'@5<rbcpu@503cpuarm,cortex-a12'@5<rbopp-table-0operating-points-v2jbopp-126000000u| opp-216000000u | opp-408000000uQ| opp-600000000u#F| opp-696000000u)||~opp-816000000u0,|B@opp-1008000000u<|opp-1200000000uG|opp-1416000000uTfr|Oopp-1512000000uZJ|opp-1608000000u_"| opp-1704000000ue|popp-1800000000ukI|\reserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mb timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H 5a  pclktimerdisplay-subsystemrockchip,display-subsystem mmc@ff0c0000rockchip,rk3288-dw-mshcр 5Drvbiuciuciu-driveciu-sample  @'reset 3disabledmmc@ff0d0000rockchip,rk3288-dw-mshcр 5Eswbiuciuciu-driveciu-sample ! @'reset3okay:DUbx default mmc@ff0e0000rockchip,rk3288-dw-mshcр 5Ftxbiuciuciu-driveciu-sample "@'reset 3disabledmmc@ff0f0000rockchip,rk3288-dw-mshcр 5Guybiuciuciu-driveciu-sample #@'reset3okay: '2xdefault saradc@ff100000rockchip,saradc $A5I[saradcapb_pclkW 'saradc-apb 3disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARspiclkapb_pclkS  Xtxrx ,default 3disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSspiclkapb_pclkS Xtxrx -default 3disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTspiclkapb_pclkSXtxrx .default !"#3okayb flash@0jedec,spi-norui2c@ff140000rockchip,rk3288-i2c >i2c5Mdefault$3okay2dtpm@20infineon,slb9645tt i2c@ff150000rockchip,rk3288-i2c ?i2c5Odefault% 3disabledi2c@ff160000rockchip,rk3288-i2c @i2c5Pdefault&3okay2,i2c@ff170000rockchip,rk3288-i2c Ai2c5Qdefault' 3disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 75MUbaudclkapb_pclkSXtxrxdefault ()*3okaybluetoothdefault +,-brcm,bcm43540-bt . . .-$serial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 85NVbaudclkapb_pclkSXtxrxdefault/3okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 95OWbaudclkapb_pclkdefault03okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :5PXbaudclkapb_pclkSXtxrxdefault1 3disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;5QYbaudclkapb_pclkS  Xtxrxdefault2 3disableddma-controller@ff250000arm,pl330arm,primecell%@;Fa5 apb_pclkbthermal-zonesreserve-thermalx3cpu-thermalxd3tripscpu_alert0ppassiveb4cpu_alert1$passiveb5cpu_crit criticalcooling-mapsmap040map150gpu-thermalxd3tripsgpu_alert04passiveb6gpu_crit criticalcooling-mapsmap06 7tsadc@ff280000rockchip,rk3288-tsadc( %5HZtsadcapb_pclk 'tsadc-apbinitdefaultsleep898:H3okay%<b3ethernet@ff290000rockchip,rk3288-gmac)Wmacirqeth_wake_irq:85fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB 'stmmaceth 3disabledusb@ff500000 generic-ehciP 5g;lusb3okayvusb@ff520000 generic-ohciR )5g;lusb 3disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 5otghostg< lusb2-phy3okayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 5otghost@@ g= lusb2-phy3okayz=usb@ff5c0000 generic-ehci\ 5 3disableddma-controller@ff600000arm,pl330arm,primecell`@;Fa5 apb_pclk 3disabledi2c@ff650000rockchip,rk3288-i2ce <i2c5Ldefault>3okay2dpmic@1brockchip,rk808xin32kwifibt_32kin&?default @AB:HT`lxCD DbregulatorsDCDC_REG1vdd_arm q qb regulator-state-mem.DCDC_REG2vdd_gpu 5qburegulator-state-mem.DCDC_REG3 vcc135_ddrregulator-state-memGDCDC_REG4vcc_18w@w@bregulator-state-memG_w@LDO_REG3vdd_10B@B@regulator-state-memG_B@LDO_REG7 vdd10_lcdB@B@{regulator-state-mem.SWITCH_REG1 vcc33_lcdbXregulator-state-mem.SWITCH_REG2 vcc18_hdmi{i2c@ff660000rockchip,rk3288-i2cf =i2c5NdefaultE3okay2 pwm@ff680000rockchip,rk3288-pwmhdefaultF5_ 3disabledpwm@ff680010rockchip,rk3288-pwmhdefaultG5_3okaybpwm@ff680020rockchip,rk3288-pwmh defaultH5_ 3disabledpwm@ff680030rockchip,rk3288-pwmh0defaultI5_ 3disabledsram@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsbpower-controller!rockchip,rk3288-power-controllerh b\power-domain@9 5chgfdehilkj$JKLMNOPQRpower-domain@11 5opSTpower-domain@12 5Upower-domain@13 5VWreboot-modesyscon-reboot-modeRBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv5 xin24m:Hjk$ #gׄeрxhрxhbsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwb:edp-phyrockchip,rk3288-dp-phy5h24m 3disabledblio-domains"rockchip,rk3288-io-voltage-domain3okay*C4?MC]CkXwusbphyrockchip,rk3288-usb-phy3okayusb-phy@320 5]phyclk 'phy-resetb=usb-phy@33445^phyclk 'phy-resetb;usb-phy@348H5_phyclk 'phy-resetb<watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt5p O3okaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif5T mclkhclkSYXtx 6defaultZ: 3disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 55Ri2s_clki2s_hclkSYYXtxrxdefault[ 3disabledcrypto@ff8a0000rockchip,rk3288-crypto@ 0 5}aclkhclksclkapb_pclk 'crypto-rstiommu@ff900800rockchip,iommu@ 5 aclkiface 3disablediommu@ff914000rockchip,iommu @P 5 aclkiface 3disabledrga@ff920000rockchip,rk3288-rga 5jaclkhclksclk\ ilm 'coreaxiahbvop@ff930000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vop\ def 'axiahbdclk]3okayportb endpoint@0 ^bqendpoint@1 _bmendpoint@2 `bgendpoint@3 abjiommu@ff930300rockchip,iommu 5 aclkiface\ 3okayb]vop@ff940000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vop\  'axiahbdclkb 3disabledportb endpoint@0 cbrendpoint@1 dbnendpoint@2 ebhendpoint@3 fbkiommu@ff940300rockchip,iommu 5 aclkiface\  3disabledbbmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 5~d refpclk\ : 3disabledportsportendpoint@0 gb`endpoint@1 hbelvds@ff96c000rockchip,rk3288-lvds@5g pclk_lvdslcdci\ : 3disabledportsport@0endpoint@0 jbaendpoint@1 kbfdp@ff970000rockchip,rk3288-dp@ b5icdppclkglldpo'dp: 3disabledportsport@0endpoint@0 mb_endpoint@1 nbdhdmi@ff980000rockchip,rk3288-dw-hdmi: g5hmniahbisfrcec\ 3okaydefaultunwedgeopportsportendpoint@0 qb^endpoint@1 rbcvideo-codec@ff9a0000rockchip,rk3288-vpu   Wvepuvdpu5 aclkhclks\ iommu@ff9a0800rockchip,iommu 5 aclkiface\ bsiommu@ff9c0440rockchip,iommu @@@ o5 aclkiface 3disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ Wjobmmugpu5t\ 3okay ub7opp-table-1operating-points-v2btopp-100000000u|~opp-200000000u |~opp-300000000u|B@opp-400000000uׄ|opp-600000000u#F|qos@ffaa0000rockchip,rk3288-qossyscon bVqos@ffaa0080rockchip,rk3288-qossyscon bWqos@ffad0000rockchip,rk3288-qossyscon bKqos@ffad0100rockchip,rk3288-qossyscon bLqos@ffad0180rockchip,rk3288-qossyscon bMqos@ffad0400rockchip,rk3288-qossyscon bNqos@ffad0480rockchip,rk3288-qossyscon bOqos@ffad0500rockchip,rk3288-qossyscon bJqos@ffad0800rockchip,rk3288-qossyscon bPqos@ffad0880rockchip,rk3288-qossyscon bQqos@ffad0900rockchip,rk3288-qossyscon bRqos@ffae0000rockchip,rk3288-qossyscon bUqos@ffaf0000rockchip,rk3288-qossyscon bSqos@ffaf0080rockchip,rk3288-qossyscon bTdma-controller@ffb20000arm,pl330arm,primecell@;Fa5 apb_pclkbYefuse@ffb40000rockchip,rk3288-efuse 5q pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400 " 7@ @ `   bpinctrlrockchip,rk3288-pinctrl:default vwxgpio@ff750000rockchip,gpio-banku Q5@ H X " 7b?gpio@ff780000rockchip,gpio-bankx R5A H X " 7gpio@ff790000rockchip,gpio-banky S5B H X " 7bgpio@ff7a0000rockchip,gpio-bankz T5C H X " 7gpio@ff7b0000rockchip,gpio-bank{ U5D H X " 7b.gpio@ff7c0000rockchip,gpio-bank| V5E H X " 7gpio@ff7d0000rockchip,gpio-bank} W5F H X " 7gpio@ff7e0000rockchip,gpio-bank~ X5G H X " 7bDgpio@ff7f0000rockchip,gpio-bank Y5H H X " 7hdmihdmi-cec-c0 dyhdmi-cec-c7 dyhdmi-ddc dyybohdmi-ddc-unwedge dzybpvcc50-hdmi-en dybpcfg-output-low rbzpcfg-pull-up }b{pcfg-pull-down b|pcfg-pull-none bypcfg-pull-none-12ma  bsuspendglobal-pwroff dybxddrio-pwroff dybwddr0-retention d{bvddr1-retention d{edpedp-hpd d |i2c0i2c0-xfer dyyb>i2c1i2c1-xfer dyyb$i2c2i2c2-xfer d y ybEi2c3i2c3-xfer dyyb%i2c4i2c4-xfer dyyb&i2c5i2c5-xfer dyyb'i2s0i2s0-bus` dyyyyyyb[lcdclcdc-ctl@ dyyyybisdmmcsdmmc-clk dysdmmc-cmd d{sdmmc-cd d{sdmmc-bus1 d{sdmmc-bus4@ d{{{{sdio0sdio0-bus1 d{sdio0-bus4@ d}}}}bsdio0-cmd d}bsdio0-clk d}bsdio0-cd d{sdio0-wp d{sdio0-pwr d{sdio0-bkpwr d{sdio0-int d{wifienable-h dybbt-enable-l dyb,bt-host-wake d|bt-host-wake-l dyb+bt-dev-wake-sleep dzbt-dev-wake-awake d~bt-dev-wake dyb-sdio1sdio1-bus1 d{sdio1-bus4@ d{{{{sdio1-cd d{sdio1-wp d{sdio1-bkpwr d{sdio1-int d{sdio1-cmd d{sdio1-clk dysdio1-pwr d {emmcemmc-clk d}bemmc-cmd d}bemmc-pwr d {emmc-bus1 d{emmc-bus4@ d{{{{emmc-bus8 d}}}}}}}}bemmc-reset d ybspi0spi0-clk d {bspi0-cs0 d {bspi0-tx d{bspi0-rx d{bspi0-cs1 d{spi1spi1-clk d {bspi1-cs0 d {bspi1-rx d{bspi1-tx d{bspi2spi2-cs1 d{spi2-clk d{b spi2-cs0 d{b#spi2-rx d{b"spi2-tx d {b!uart0uart0-xfer d{yb(uart0-cts d{b)uart0-rts dyb*uart1uart1-xfer d{ yb/uart1-cts d {uart1-rts d yuart2uart2-xfer d{yb0uart3uart3-xfer d{yb1uart3-cts d {uart3-rts d yuart4uart4-xfer d{yb2uart4-cts d {uart4-rts d ytsadcotp-pin d yb8otp-out d yb9pwm0pwm0-pin dybFpwm1pwm1-pin dybGpwm2pwm2-pin dybHpwm3pwm3-pin dybIgmacrgmii-pins dyyyyyyy yyrmii-pins dyyyyyyyyyyspdifspdif-tx d ybZpcfg-pull-none-drv-8ma  b}pcfg-pull-up-drv-8ma } pcfg-output-high b~buttonspwr-key-l d{bpmicpmic-int-l d{b@dvs-1 d |bAdvs-2 d|bBrebootap-warm-reset-h d ybrecovery-switchrec-mode-l d {tpmtpm-int-h dywrite-protectfw-wp-ap dyusb-hostusb2-pwr-en d ybchosen serial2:115200n8memorymemorypower-button gpio-keysdefaultkey-power Power ? t d:gpio-restart gpio-restart ? default emmc-pwrseqmmc-pwrseq-emmcdefault bsdio-pwrseqmmc-pwrseq-simple5 ext_clockdefault .b vcc-5vregulator-fixedvcc_5vLK@LK@bvcc33-sysregulator-fixed vcc33_sys2Z2Z bvcc50-hdmiregulator-fixed vcc50_hdmi   #Ddefaultvdd-logicpwm-regulator vdd_logic ( - 8{ L~pvcc33_ioregulator-fixed vcc33_io bCvcc5-host2-regulatorregulator-fixed  #? default vcc5_host2 #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablepinctrl-namespinctrl-0sd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplycap-mmc-highspeedrockchip,default-sample-phasedisable-wpmmc-hs200-1_8v#io-channel-cellsdmasdma-namesrx-sample-delay-nsspi-max-frequencyi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedreg-shiftreg-io-widthhost-wakeup-gpiosshutdown-gpiosdevice-wakeup-gpiosmax-speedbrcm,bt-pcm-int-params#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clocksassigned-clock-parentsrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplydvs-gpiosregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltregulator-suspend-mem-disabled#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplyenable-active-highgpiopwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unit