8P( Kgoogle,veyron-pinky-rev2google,veyron-pinkygoogle,veyronrockchip,rk3288& 7Google Pinkyaliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000/spi@ff110000/ec@0/i2c-tunnelarm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12 -@;Br\ hcpu@501cpuarm,cortex-a12 -@;Brhcpu@502cpuarm,cortex-a12 -@;Brhcpu@503cpuarm,cortex-a12 -@;Brhopp-table-0operating-points-v2phopp-126000000{ opp-216000000{  opp-408000000{Q opp-600000000{#F opp-696000000{)|~opp-816000000{0,B@opp-1008000000{<opp-1200000000{Gopp-1416000000{TfrOopp-1512000000{ZJopp-1608000000{_" opp-1704000000{epopp-1800000000{kI\reserved-memorydma-unusable@fe000000oscillator fixed-clockn6xin24mh timerarm,armv7-timer0   n6timer@ff810000rockchip,rk3288-timer  H ;a  pclktimerdisplay-subsystemrockchip,display-subsystem mmc@ff0c0000rockchip,rk3288-dw-mshcр ;Drvbiuciuciu-driveciu-sample"  @-reset9okay@J\m  Zdefault  mmc@ff0d0000rockchip,rk3288-dw-mshcр ;Eswbiuciuciu-driveciu-sample" ! @-reset9okay@\"8Cdefault mmc@ff0e0000rockchip,rk3288-dw-mshcр ;Ftxbiuciuciu-driveciu-sample" "@-reset 9disabledmmc@ff0f0000rockchip,rk3288-dw-mshcр ;Guybiuciuciu-driveciu-sample" #@-reset9okay@JQ\Cdefaultsaradc@ff100000rockchip,saradc $k;I[saradcapb_pclkW -saradc-apb 9disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi;ARspiclkapb_pclk} txrx ,default!"#$9okayec@0google,cros-ec-spi& default%-i2c-tunnelgoogle,cros-ec-i2c-tunnelsbs-battery@bsbs,sbs-battery keyboard-controllergoogle,cros-ec-keyb D3;<=>?@A B CD}0Y1 d"#(  \V |})   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g ispi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi;BSspiclkapb_pclk} txrx -default&'() 9disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi;CTspiclkapb_pclk}  txrx .default*+,-9okay@ flash@0jedec,spi-nori2c@ff140000rockchip,rk3288-i2c >i2c;Mdefault.9okayS2kdtpm@20infineon,slb9645tt i2c@ff150000rockchip,rk3288-i2c ?i2c;Odefault/9okayS2k,i2c@ff160000rockchip,rk3288-i2c @i2c;Pdefault09okayS2k,ts3a227e@3b ti,ts3a227e;&1default2htrackpad@15elan,ekth3000& default34i2c@ff170000rockchip,rk3288-i2c Ai2c;Qdefault5 9disabledserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7;MUbaudclkapb_pclk}  txrxdefault 6789okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8;NVbaudclkapb_pclk}  txrxdefault99okayserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9;OWbaudclkapb_pclkdefault:9okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart :;PXbaudclkapb_pclk}  txrxdefault; 9disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ;;QYbaudclkapb_pclk} txrxdefault< 9disableddma-controller@ff250000arm,pl330arm,primecell%@; apb_pclkh thermal-zonesreserve-thermal(6=cpu-thermald(6=tripscpu_alert0FpRpassiveh>cpu_alert1F$Rpassiveh?cpu_critFR criticalcooling-mapsmap0]>0bmap1]?0bgpu-thermald(6=tripsgpu_alert0F4Rpassiveh@gpu_critFR criticalcooling-mapsmap0]@ bAtsadc@ff280000rockchip,rk3288-tsadc( %;HZtsadcapb_pclk -tsadc-apbinitdefaultsleepBqC{BDH 9disabledh=ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irqD8;fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB -stmmaceth 9disabledusb@ff500000 generic-ehciP ;Eusb9okayusb@ff520000 generic-ohciR );Eusb 9disabledusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T ;otg&hostF usb2-phy.9okayEusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X ;otg&host\n}@@ G usb2-phy9okayzGEusb@ff5c0000 generic-ehci\ ; 9disableddma-controller@ff600000arm,pl330arm,primecell`@; apb_pclk 9disabledi2c@ff650000rockchip,rk3288-i2ce <i2c;LdefaultH9okayS2kdpmic@1brockchip,rk808xin32kwifibt_32kin&1defaultIJ(54BOJ[JhregulatorsDCDC_REG1hvdd_armw q qh regulator-state-memDCDC_REG2hvdd_gpuw 5qhregulator-state-memDCDC_REG3 hvcc135_ddrwregulator-state-memDCDC_REG4hvcc_18ww@w@hregulator-state-memw@LDO_REG1 hvcc33_iow2Z2Zh4regulator-state-mem2ZLDO_REG3hvdd_10wB@B@regulator-state-memB@LDO_REG7hvdd10_lcd_pwren_hw&%&%regulator-state-memSWITCH_REG1 hvcc33_lcdwh`regulator-state-memLDO_REG6 hvcc18_codecww@w@haregulator-state-memLDO_REG4 hvccio_sdw@2Zhregulator-state-memLDO_REG5 hvcc33_sd2Z2Zhregulator-state-memLDO_REG8 hvcc33_ccdw2Z2Zregulator-state-memSWITCH_REG2w hvcc18_lcdregulator-state-memi2c@ff660000rockchip,rk3288-i2cf =i2c;NdefaultK9okayS2k max98090@10maxim,max98090&Lmclk;qdefaultMhpwm@ff680000rockchip,rk3288-pwmh/defaultN;_9okayhpwm@ff680010rockchip,rk3288-pwmh/defaultO;_9okayhpwm@ff680020rockchip,rk3288-pwmh /defaultP;_ 9disabledpwm@ff680030rockchip,rk3288-pwmh0/defaultQ;_ 9disabledsram@ff700000 mmio-sramppsmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdshpower-controller!rockchip,rk3288-power-controller:h hepower-domain@9 ;chgfdehilkj$NRSTUVWXYZ:power-domain@11 ;opN[\:power-domain@12 ;N]:power-domain@13 ;N^_:reboot-modesyscon-reboot-modeU\RBhRBvRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv; xin24mDHjk$#gׄeрxhрxhhsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwhDedp-phyrockchip,rk3288-dp-phy;h24m9okayhuio-domains"rockchip,rk3288-io-voltage-domain9okay444 `  a %usbphyrockchip,rk3288-usb-phy9okayusb-phy@320 ;]phyclk -phy-resethGusb-phy@3344;^phyclk -phy-resethEusb-phy@348H;_phyclk -phy-resethFwatchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt;p O9okaysound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif 3;T mclkhclk}btx 6defaultcD 9disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s 3 5;Ri2s_clki2s_hclk}bbtxrxdefaultd D _9okayhcrypto@ff8a0000rockchip,rk3288-crypto@ 0 ;}aclkhclksclkapb_pclk -crypto-rstiommu@ff900800rockchip,iommu@ ; aclkiface y 9disablediommu@ff914000rockchip,iommu @P ; aclkiface y  9disabledrga@ff920000rockchip,rk3288-rga ;jaclkhclksclk e ilm -coreaxiahbvop@ff930000rockchip,rk3288-vop  ;aclk_vopdclk_vophclk_vop e def -axiahbdclk f9okayporth endpoint@0 gh{endpoint@1 hhvendpoint@2 ihpendpoint@3 jhsiommu@ff930300rockchip,iommu ; aclkiface e  y9okayhfvop@ff940000rockchip,rk3288-vop  ;aclk_vopdclk_vophclk_vop e  -axiahbdclk k9okayporth endpoint@0 lh|endpoint@1 mhwendpoint@2 nhqendpoint@3 ohtiommu@ff940300rockchip,iommu ; aclkiface e  y9okayhkmipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ ;~d refpclk e D 9disabledportsportendpoint@0 phiendpoint@1 qhnlvds@ff96c000rockchip,rk3288-lvds@;g pclk_lvdslcdcr e D 9disabledportsport@0endpoint@0 shjendpoint@1 thodp@ff970000rockchip,rk3288-dp@ b;icdppclkudpo-dpD9okay portsport@0endpoint@0 vhhendpoint@1 whmport@1endpoint@0 xhhdmi@ff980000rockchip,rk3288-dw-hdmi 3D g;hmniahbisfrcec e 9okaydefaultunwedgeyqzhportsportendpoint@0 {hgendpoint@1 |hlvideo-codec@ff9a0000rockchip,rk3288-vpu   vepuvdpu; aclkhclk } e iommu@ff9a0800rockchip,iommu ; aclkiface y e h}iommu@ff9c0440rockchip,iommu @@@ o; aclkiface y 9disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ jobmmugpu; ~ e 9okay hAopp-table-1operating-points-v2h~opp-100000000{~opp-200000000{ ~opp-300000000{B@opp-400000000{ׄopp-600000000{#Fqos@ffaa0000rockchip,rk3288-qossyscon h^qos@ffaa0080rockchip,rk3288-qossyscon h_qos@ffad0000rockchip,rk3288-qossyscon hSqos@ffad0100rockchip,rk3288-qossyscon hTqos@ffad0180rockchip,rk3288-qossyscon hUqos@ffad0400rockchip,rk3288-qossyscon hVqos@ffad0480rockchip,rk3288-qossyscon hWqos@ffad0500rockchip,rk3288-qossyscon hRqos@ffad0800rockchip,rk3288-qossyscon hXqos@ffad0880rockchip,rk3288-qossyscon hYqos@ffad0900rockchip,rk3288-qossyscon hZqos@ffae0000rockchip,rk3288-qossyscon h]qos@ffaf0000rockchip,rk3288-qossyscon h[qos@ffaf0080rockchip,rk3288-qossyscon h\dma-controller@ffb20000arm,pl330arm,primecell@; apb_pclkhbefuse@ffb40000rockchip,rk3288-efuse ;q pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400  @ @ `   hpinctrlrockchip,rk3288-pinctrlDdefaultsleepqgpio@ff750000rockchip,gpio-banku Q;@    h1gpio@ff780000rockchip,gpio-bankx R;A    gpio@ff790000rockchip,gpio-banky S;B    gpio@ff7a0000rockchip,gpio-bankz T;C    gpio@ff7b0000rockchip,gpio-bank{ U;D    hgpio@ff7c0000rockchip,gpio-bank| V;E    gpio@ff7d0000rockchip,gpio-bank} W;F    hLgpio@ff7e0000rockchip,gpio-bank~ X;G    h gpio@ff7f0000rockchip,gpio-bank Y;H    hdmihdmi-cec-c0 hdmi-cec-c7 hdmi-ddc hyhdmi-ddc-unwedge hzpcfg-output-low ,hpcfg-pull-up 7hpcfg-pull-down Dhpcfg-pull-none Shpcfg-pull-none-12ma S ` hsuspendglobal-pwroff hddrio-pwroff hddr0-retention hddr1-retention suspend-l-wake hsuspend-l-sleep hedpedp-hpd  i2c0i2c0-xfer hHi2c1i2c1-xfer h.i2c2i2c2-xfer   hKi2c3i2c3-xfer h/i2c4i2c4-xfer h0i2c5i2c5-xfer h5i2s0i2s0-bus` hdlcdclcdc-ctl@ hrsdmmcsdmmc-clk hsdmmc-cmd hsdmmc-cd sdmmc-bus1 sdmmc-bus4@ hsdmmc-cd-disabled hsdmmc-cd-pin hsdmmc-wp-pin  hsdio0sdio0-bus1 sdio0-bus4@ hsdio0-cmd hsdio0-clk hsdio0-cd sdio0-wp sdio0-pwr sdio0-bkpwr sdio0-int wifienable-h hbt-enable-l bt-host-wake bt-host-wake-l bt-dev-wake-sleep hbt-dev-wake-awake hbt-dev-wake sdio1sdio1-bus1 sdio1-bus4@ sdio1-cd sdio1-wp sdio1-bkpwr sdio1-int sdio1-cmd sdio1-clk sdio1-pwr  emmcemmc-clk hemmc-cmd hemmc-pwr  emmc-bus1 emmc-bus4@ emmc-bus8 hemmc-reset  hspi0spi0-clk  h!spi0-cs0  h$spi0-tx h"spi0-rx h#spi0-cs1 spi1spi1-clk  h&spi1-cs0  h)spi1-rx h(spi1-tx h'spi2spi2-cs1 spi2-clk h*spi2-cs0 h-spi2-rx h,spi2-tx  h+uart0uart0-xfer h6uart0-cts h7uart0-rts h8uart1uart1-xfer  h9uart1-cts  uart1-rts  uart2uart2-xfer h:uart3uart3-xfer h;uart3-cts  uart3-rts  uart4uart4-xfer h<uart4-cts  uart4-rts  tsadcotp-pin  hBotp-out  hCpwm0pwm0-pin hNpwm1pwm1-pin hOpwm2pwm2-pin hPpwm3pwm3-pin hQgmacrgmii-pins  rmii-pins spdifspdif-tx  hcpcfg-pull-none-drv-8ma S `hpcfg-pull-up-drv-8ma 7 `pcfg-output-high ohbuttonspwr-key-l hap-lid-int-l hpwr-key-h hpmicpmic-int-l hIrebootap-warm-reset-h  hrecovery-switchrec-mode-l  tpmtpm-int-h write-protectfw-wp-ap codechp-det hint-codec hMmic-det  hheadsetts3a227e-int-l h2backlightbl-en hchargerac-present-ap hcros-ecec-int h%trackpadtrackpad-int h3usb-hosthost1-pwr-en  husbotg-pwren-h  hchosen {serial2:115200n8memorymemorypower-button gpio-keysdefaultpower Power 1 t dgpio-restart gpio-restart 1 default sdio-pwrseqmmc-pwrseq-simple; ext_clockdefault hvcc-5vregulator-fixedhvcc_5vwLK@LK@ hJvcc33-sysregulator-fixed hvcc33_sysw2Z2Z hvcc50-hdmiregulator-fixed hvcc50_hdmiw Jvdd-logicpwm-regulator hvdd_logic   { w~psound!rockchip,rockchip-audio-max98090default VEYRON-I2S  ( =L SL  j backlightpwm-backlight    default B@  hpanelinnolux,n116bge9okay ` panel-timingl !V ) 6< B L Y a n  z  portsportendpoint hxgpio-charger gpio-charger mains 1defaultlid-switch gpio-keysdefaultlid Lid 1   power 1vccsysregulator-fixedhvccsyswhvcc5-host1-regulatorregulator-fixed  1 default hvcc5_host1wvcc5v-otg-regulatorregulator-fixed  1 default hvcc5_host2w #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2i2c20interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientcpu0-supplyphandleopp-sharedopp-hzopp-microvoltrangesclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendclock-namesportsmax-frequencyfifo-depthreset-namesstatusbus-widthcap-mmc-highspeedcap-sd-highspeedcard-detect-delaycd-gpiosrockchip,default-sample-phasesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplypinctrl-namespinctrl-0wp-gpioscap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removabledisable-wpmmc-hs200-1_8v#io-channel-cellsdmasdma-namesgoogle,cros-ec-spi-pre-delayspi-max-frequencygoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countkeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymaprx-sample-delay-nsi2c-scl-falling-time-nsi2c-scl-rising-time-nspowered-while-suspendedti,micbiasvcc-supplywakeup-sourcereg-shiftreg-io-width#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polarityinterrupt-namesphysphy-namesneeds-reset-on-resumedr_modesnps,reset-phy-on-wakesnps,need-phy-for-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizeassigned-clocksassigned-clock-parentsrockchip,system-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc12-supplyvddio-supplyvcc10-supplyvcc9-supplyvcc11-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplydvp-supplyflash0-supplygpio1830-supplygpio30-supplylcdc-supplywifi-supplyaudio-supplysdcard-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointforce-hpdmali-supplyinterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highstdout-pathlabellinux,codedebounce-intervalpriorityreset-gpiosvin-supplypwmspwm-supplypwm-dutycycle-rangepwm-dutycycle-unitrockchip,modelrockchip,i2s-controllerrockchip,audio-codecrockchip,hp-det-gpiosrockchip,mic-det-gpiosrockchip,headset-codecrockchip,hdmi-codecbrightness-levelsnum-interpolated-stepsdefault-brightness-levelenable-gpiospost-pwm-on-delay-mspwm-off-delay-mspower-supplybacklighthactivehfront-porchhback-porchhsync-lenhsync-activevactivevfront-porchvback-porchvsync-lenvsync-activecharger-typelinux,input-typeenable-active-highgpio