08ɀ( H'firefly,firefly-rk3399rockchip,rk3399 +7Firefly-RK3399 Boardaliases=/ethernet@fe300000G/i2c@ff3c0000L/i2c@ff110000Q/i2c@ff120000V/i2c@ff130000[/i2c@ff3d0000`/i2c@ff140000e/i2c@ff150000j/i2c@ff160000o/i2c@ff3e0000t/serial@ff180000|/serial@ff190000/serial@ff1a0000/serial@ff1b0000/serial@ff370000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1cpu@0cpuarm,cortex-a53arm,armv8pscid   cpu@1cpuarm,cortex-a53arm,armv8pscid   cpu@2cpuarm,cortex-a53arm,armv8pscid   cpu@3cpuarm,cortex-a53arm,armv8pscid   cpu@100cpuarm,cortex-a72arm,armv8psci    cpu@101cpuarm,cortex-a72arm,armv8psci    display-subsystemrockchip,display-subsystem pmu_a53arm,cortex-a53-pmupmu_a72arm,cortex-a72-pmupsci arm,psci-1.0smctimerarm,armv8-timer@   &xin24m fixed-clock=n6Mxin24m`amba simple-bus+mdma-controller@ff6d0000arm,pl330arm,primecellm@ t apb_pclk dma-controller@ff6e0000arm,pl330arm,primecelln@ t apb_pclkpcie@f8000000rockchip,rk3399-pcie axi-baseapb-base+ Gaclkaclk-perfhclkpm0123syslegacyclient`  ,pcie-phy-0pcie-phy-1pcie-phy-2pcie-phy-38m8$(+coremgmtmgmt-stickypipepmpclkaclk7okay >GQdefault_interrupt-controlleri ethernet@fe300000rockchip,rk3399-gmac0 macirq8ighfjfMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac~$ +stmmaceth7okayinputrgmiiQdefault_  'P(%dwmmc@fe3100000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshc1@@.р Mbiuciuciu-driveciu-sample<~$y+reset 7disableddwmmc@fe3200000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshc2@A.рG  Lbiuciuciu-driveciu-sample<~$z+reset7okay\fx Qdefault _sdhci@fe330000+rockchip,rk3399-sdhci-5.1arasan,sdhci-5.13 NG Nclk_xinclk_ahbMemmc_cardclock`  phy_arasan~7okay\ usb@fe380000 generic-ehci8!usbhostarbiterutmi"usb7okayusb@fe3a0000 generic-ohci:!usbhostarbiterutmi"usb7okayusb@fe3c0000 generic-ehci<#usbhostarbiterutmi$usb7okayusb@fe3e0000 generic-ohci> #usbhostarbiterutmi$usb7okayusb@fe800000rockchip,rk3399-dwc3+m0Gref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clk$% +usb3-otg7okaydwc3 snps,dwc3iotg%&usb2-phyusb3-phy utmi_wide4Mn~7okayusb@fe900000rockchip,rk3399-dwc3+m0Gref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clk$& +usb3-otg7okaydwc3 snps,dwc3nhost'(usb2-phyusb3-phy utmi_wide4Mn~7okaydp@fec00000rockchip,rk3399-cdn-dp rG  ruocore-clkpclkspdifgrf)*~ $HJ+spdifdptxapbcore 7disabledportsport+endpoint@0+ endpoint@1, interrupt-controller@fee00000 arm,gic-v3+miP   interrupt-controller@fee20000arm,gic-v3-its ppi-partitionsinterrupt-partition-0 interrupt-partition-1 saradc@ff100000rockchip,rk3399-saradc>Pesaradcapb_pclk$ +saradc-apb7okay-i2c@ff110000rockchip,rk3399-i2cAG AU i2cpclk;Qdefault_.+7okay,rt5640@1crealtek,rt5640YmclkQdefault_/ i2c@ff120000rockchip,rk3399-i2cBG BV i2cpclk#Qdefault_0+ 7disabledi2c@ff130000rockchip,rk3399-i2cCG CW i2cpclk"Qdefault_1+7okay i2c@ff140000rockchip,rk3399-i2cDG DX i2cpclk&Qdefault_2+ 7disabledi2c@ff150000rockchip,rk3399-i2cEG EY i2cpclk%Qdefault_3+ 7disabledi2c@ff160000rockchip,rk3399-i2cFG FZ i2cpclk$Qdefault_4+ 7disabledserial@ff180000&rockchip,rk3399-uartsnps,dw-apb-uartQ`baudclkapb_pclkc/9Qdefault_567okayserial@ff190000&rockchip,rk3399-uartsnps,dw-apb-uartRabaudclkapb_pclkb/9Qdefault_7 7disabledserial@ff1a0000&rockchip,rk3399-uartsnps,dw-apb-uartSbbaudclkapb_pclkd/9Qdefault_87okayserial@ff1b0000&rockchip,rk3399-uartsnps,dw-apb-uartTcbaudclkapb_pclke/9Qdefault_9 7disabledspi@ff1c0000(rockchip,rk3399-spirockchip,rk3066-spiG[spiclkapb_pclkDQdefault_:;<=+ 7disabledspi@ff1d0000(rockchip,rk3399-spirockchip,rk3066-spiH\spiclkapb_pclk5Qdefault_>?@A+ 7disabledspi@ff1e0000(rockchip,rk3399-spirockchip,rk3066-spiI]spiclkapb_pclk4Qdefault_BCDE+ 7disabledspi@ff1f0000(rockchip,rk3399-spirockchip,rk3066-spiJ^spiclkapb_pclkCQdefault_FGHI+ 7disabledspi@ff200000(rockchip,rk3399-spirockchip,rk3066-spi K_spiclkapb_pclkQdefault_JKLM~+ 7disabledthermal-zonescpuFd\jNtripscpu_alert0zppassive Ocpu_alert1z$passive Pcpu_critzs criticalcooling-mapsmap0O map1PgpuFd\jNtripsgpu_alert0z$passive Qgpu_critzs criticalcooling-mapsmap0Q tsadc@ff260000rockchip,rk3399-tsadc&aOG qOdtsadcapb_pclk$ +tsadc-apbsQinitdefaultsleep_RSR7okay Nqos@ffa58000syscon  [qos@ffa5c000syscon  \qos@ffa60080syscon qos@ffa60100syscon qos@ffa60180syscon qos@ffa70000syscon  _qos@ffa70080syscon  `qos@ffa74000syscon@  ]qos@ffa76000syscon`  ^qos@ffa90000syscon  aqos@ffa98000syscon  Tqos@ffaa0000syscon  bqos@ffaa0080syscon  cqos@ffaa8000syscon  dqos@ffaa8080syscon  eqos@ffab0000syscon  Uqos@ffab0080syscon  Vqos@ffab8000syscon  Wqos@ffac0000syscon  Xqos@ffac0080syscon  Yqos@ffac8000syscon  fqos@ffac8080syscon  gqos@ffad0000syscon  hqos@ffad8080syscon qos@ffae0000syscon  Zpower-management@ff310000&rockchip,rk3399-pmusysconsimple-mfd1power-controller!rockchip,rk3399-power-controller+ pd_iep@34",Tpd_rga@33!,UVpd_vcodec@31,Wpd_vdu@32 ,XYpd_gpu@35#,Zpd_edp@25lpd_emmc@23,[pd_gmac@22f,\pd_sd@27L,]pd_sdioaudio@28,^pd_usb3@24,_`pd_vio@15+pd_hdcp@21r,apd_isp0@19,bcpd_isp1@20,depd_tcpc0@RK3399_PD_TCPC0~}pd_tcpc1@RK3399_PD_TCPC1 pd_vo@16+pd_vopb@17,fgpd_vopl@18,hsyscon@ff320000)rockchip,rk3399-pmugrfsysconsimple-mfd2+ |io-domains&rockchip,rk3399-pmu-io-voltage-domain7okay3ispi@ff350000(rockchip,rk3399-spirockchip,rk3066-spi5jjspiclkapb_pclk<Qdefault_klmn+ 7disabledserial@ff370000&rockchip,rk3399-uartsnps,dw-apb-uart7jj"baudclkapb_pclkf/9Qdefault_o 7disabledi2c@ff3c0000rockchip,rk3399-i2c<j G j j i2cpclk9Qdefault_p+7okay=pmic@1brockchip,rk808 q`Mxin32krk808-clkout2Qdefault_rBcqs}ssssstssstu regulatorsDCDC_REG1 vdd_center(: qRpjqregulator-state-memDCDC_REG2 vdd_cpu_l(: qRpjq regulator-state-memDCDC_REG3vcc_ddr(regulator-state-memDCDC_REG4vcc_1v8(:w@Rw@ regulator-state-memw@LDO_REG1 vcc1v8_dvp(:w@Rw@ }regulator-state-memLDO_REG2 vcc2v8_dvp(:*R*regulator-state-memLDO_REG3 vcc1v8_pmu(:w@Rw@ uregulator-state-memw@LDO_REG4 vcc_sdio(:w@R- regulator-state-mem-LDO_REG5vcca3v0_codec(:-R-regulator-state-memLDO_REG6vcc_1v5(:`R`regulator-state-mem`LDO_REG7vcca1v8_codec(:w@Rw@ ~regulator-state-memLDO_REG8vcc_3v0(:-R- iregulator-state-mem-SWITCH_REG1 vcc3v3_s3( regulator-state-memSWITCH_REG2 vcc3v3_s0(regulator-state-memregulator@40silergy,syr827@ vdd_cpu_b: 4R`j(s regulator-state-memregulator@41silergy,syr828Avdd_gpu: 4R`j(sregulator-state-memi2c@ff3d0000rockchip,rk3399-i2c=j G j j i2cpclk8Qdefault_v+7okayXaccelerometer@68invensense,mpu6500h qi2c@ff3e0000rockchip,rk3399-i2c>j G j j i2cpclk:Qdefault_w+ 7disabledpwm@ff420000(rockchip,rk3399-pwmrockchip,rk3288-pwmBQdefault_xjpwm7okay pwm@ff420010(rockchip,rk3399-pwmrockchip,rk3288-pwmBQdefault_yjpwm 7disabledpwm@ff420020(rockchip,rk3399-pwmrockchip,rk3288-pwmB Qdefault_zjpwm7okay pwm@ff420030(rockchip,rk3399-pwmrockchip,rk3288-pwmB0Qdefault_{jpwm 7disablediommu@ff650800rockchip,iommue@svpu_mmu aclkiface 7disablediommu@ff660480rockchip,iommu f@f@u vdec_mmu aclkiface 7disablediommu@ff670800rockchip,iommug@*iep_mmu aclkiface 7disabledrga@ff680000rockchip,rk3399-rgah7maclkhclksclk$jgi +coreaxiahb~!efuse@ff690000rockchip,rk3399-efusei+} pclk_efusecpu-id@7cpu-leakage@17gpu-leakage@18center-leakage@19cpu-leakage@1alogic-leakage@1bwafer-info@1cpmu-clock-controller@ff750000rockchip,rk3399-pmucruu|` jG(J jclock-controller@ff760000rockchip,rk3399-cruv` @BCx@G#g/;рxh<4`#Fׄׄ  syscon@ff770000&rockchip,rk3399-grfsysconsimple-mfdw+ io-domains"rockchip,rk3399-io-voltage-domain7okay}&~3@iusb2-phy@e450rockchip,rk3399-usb2phyP{phyclk`Mclk_usbphy0_480m7okay !host-portP linestate7okay "otg-portP0ghjotg-bvalidotg-idlinestate7okay %usb2-phy@e460rockchip,rk3399-usb2phy`|phyclk`Mclk_usbphy1_480m7okay #host-portP linestate7okay $otg-portP0lmootg-bvalidotg-idlinestate7okay 'phy@f780rockchip,rk3399-emmc-phy$emmcclkP7okay pcie-phyrockchip,rk3399-pcie-phyrefclkP$+phy7okay phy@ff7c0000rockchip,rk3399-typec-phy|~}tcpdcoretcpdphy-ref~G~$L+uphyuphy-pipeuphy-tcphy7okaydp-portP )usb3-portP &phy@ff800000rockchip,rk3399-typec-phytcpdcoretcpdphy-refG~ $M+uphyuphy-pipeuphy-tcphy7okaydp-portP *usb3-portP (watchdog@ff848000 snps,dw-wdt|xrktimer@ff850000rockchip,rk3399-timerQhZ pclktimerspdif@ff870000rockchip,rk3399-spdifB[`tx mclkhclkUQdefault_~ 7disabledi2s@ff880000(rockchip,rk3399-i2srockchip,rk3066-i2s'[`txrxi2s_clki2s_hclkVQdefault_~7okayji2s@ff890000(rockchip,rk3399-i2srockchip,rk3066-i2s([`txrxi2s_clki2s_hclkWQdefault_~7okayj i2s@ff8a0000(rockchip,rk3399-i2srockchip,rk3066-i2s)[`txrxi2s_clki2s_hclkX~7okay vop@ff8f0000rockchip,rk3399-vop-lit>wGׄaclk_vopdclk_vophclk_vop~$ +axiahbdclk7okayport+ endpoint@0 endpoint@1 endpoint@2 endpoint@3 endpoint@4 ,iommu@ff8f3f00rockchip,iommu?w vopl_mmu aclkiface~7okay vop@ff900000rockchip,rk3399-vop-big>vGׄaclk_vopdclk_vophclk_vop~$ +axiahbdclk7okayport+ endpoint@0 endpoint@1 endpoint@2 endpoint@3 endpoint@4 +iommu@ff903f00rockchip,iommu?v vopb_mmu aclkiface~7okay iommu@ff914000rockchip,iommu @P+ isp0_mmu aclkiface 7disablediommu@ff924000rockchip,iommu @P, isp1_mmu aclkiface 7disabledhdmi-soundsimple-audio-cardi2s hdmi-sound 7disabledsimple-audio-card,cpu simple-audio-card,codec hdmi@ff940000rockchip,rk3399-dw-hdmi(tqopiahbisfrvpllgrfcec~97okay Qdefault_ portsport+endpoint@0 endpoint@1 mipi@ff960000*rockchip,rk3399-mipi-dsisnps,dw-mipi-dsi- porefpclkphy_cfggrf~$+apb 7disabledports+port@0+endpoint@0 endpoint@1 mipi@ff968000*rockchip,rk3399-mipi-dsisnps,dw-mipi-dsi. qorefpclkphy_cfggrf~$+apb 7disabledports+port@0+endpoint@0 endpoint@1 edp@ff970000rockchip,rk3399-edp jlo dppclkgrfQdefault_~$+dp 7disabledports+port@0+endpoint@0 endpoint@1 gpu@ff9a0000#rockchip,rk3399-maliarm,mali-t8600 gpujobmmu~# 7disabledpinctrlrockchip,rk3399-pinctrl !|+mgpio0@ff720000rockchip,gpio-bankrj . >i gpio1@ff730000rockchip,gpio-banksj . >i qgpio2@ff780000rockchip,gpio-bankxP . >i gpio3@ff788000rockchip,gpio-bankxQ . >i gpio4@ff790000rockchip,gpio-bankyR . >i pcfg-pull-up J pcfg-pull-down W pcfg-pull-none f pcfg-pull-none-12ma f s  pcfg-pull-none-13ma f s  pcfg-pull-none-18ma f spcfg-pull-none-20ma f spcfg-pull-up-2ma J spcfg-pull-up-8ma J spcfg-pull-up-18ma J spcfg-pull-up-20ma J spcfg-pull-down-4ma W spcfg-pull-down-8ma W spcfg-pull-down-12ma W s pcfg-pull-down-18ma W spcfg-pull-down-20ma W spcfg-output-high pcfg-output-low clockclk-32k edpedp-hpd  gmacrgmii-pins      rmii-pins      i2c0i2c0-xfer  pi2c1i2c1-xfer  .i2c2i2c2-xfer  0i2c3i2c3-xfer  1i2c4i2c4-xfer    vi2c5i2c5-xfer    2i2c6i2c6-xfer    3i2c7i2c7-xfer  4i2c8i2c8-xfer  wi2s0i2s0-2ch-bus` i2s0-8ch-bus  i2s1i2s1-2ch-busP  sdio0sdio0-bus1 sdio0-bus4@ sdio0-cmd sdio0-clk sdio0-cd sdio0-pwr sdio0-bkpwr sdio0-wp sdio0-int sdmmcsdmmc-bus1 sdmmc-bus4@     sdmmc-clk   sdmmc-cmd   sdmmc-cd sdmmc-wp sleepap-pwroff ddrio-pwroff spdifspdif-bus  spdif-bus-1 spi0spi0-clk  :spi0-cs0  =spi0-cs1 spi0-tx  ;spi0-rx  <spi1spi1-clk   >spi1-cs0   Aspi1-rx  @spi1-tx  ?spi2spi2-clk   Bspi2-cs0   Espi2-rx   Dspi2-tx   Cspi3spi3-clk  kspi3-cs0  nspi3-rx  mspi3-tx  lspi4spi4-clk  Fspi4-cs0  Ispi4-rx  Hspi4-tx  Gspi5spi5-clk  Jspi5-cs0  Mspi5-rx  Lspi5-tx  Ktestclktest-clkout0 test-clkout1 test-clkout2 tsadcotp-gpio  Rotp-out  Suart0uart0-xfer  5uart0-cts  6uart0-rts uart1uart1-xfer    7uart2auart2a-xfer  uart2buart2b-xfer uart2cuart2c-xfer  8uart3uart3-xfer  9uart3-cts uart3-rts uart4uart4-xfer  ouarthdcpuarthdcp-xfer pwm0pwm0-pin  xpwm0-pin-pull-down vop0-pwm-pin vop1-pwm-pin pwm1pwm1-pin  ypwm1-pin-pull-down pwm2pwm2-pin  zpwm2-pin-pull-down pwm3apwm3a-pin  {pwm3bpwm3b-pin hdmihdmi-i2c-xfer hdmi-cec  pciepci-clkreqn-cpm  pci-clkreqnb-cpm pcie-pwr-en  pcie-3g-drv buttonspwrbtn  lcd-panellcd-panel-reset pmicvsel1-gpio vsel2-gpio pmic-int-l  rsdio-pwrseqwifi-enable-h  rt5640rt5640-hpcon  /usb2vcc5v0-host-en  ledswork_led-gpio  diy_led-gpio  opp-table0operating-points-v2  opp00 Q 5 @opp01 #F 5opp02 0, Popp03 < Hopp04 G B@opp05 Tfr *opp-table1operating-points-v2  opp00 Q 5 @opp01 #F 5opp02 0, opp03 < Yopp04 G ~opp05 Tfr opp06 _" opp07 kI Oopp-table2operating-points-v2 opp00  5opp01 @ 5opp02 ׄ opp03 e Yopp04 #F Hopp05 / chosen serial2:1500000n8backlightpwm-backlight q  a   !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~ external-gmac-clock fixed-clock=sY@ Mclkin_gmac` dc-12vregulator-fixeddc_12v(:R gpio-keys gpio-keys !Qdefault_power ,d A >GPIO Key Power Dtcleds gpio-ledsQdefault_work-led >work Oon Adiy-led >diy Ooff A rt5640-soundsimple-audio-cardrockchip,rt5640-codeci2s- ]MicrophoneMic JackHeadphoneHeadphone JackH wMic JackMICBIAS1IN1PMic JackHeadphone JackHPOLHeadphone JackHPORsimple-audio-card,cpu simple-audio-card,codec sdio-pwrseqmmc-pwrseq-simple ext_clockQdefault_  vcc1v8-s3regulator-fixed vcc1v8_s3(:w@Rw@ -vcc3v3-pcie-regulatorregulator-fixed  qQdefault_ vcc3v3_pcie(vcc3v3-sysregulator-fixed vcc3v3_sys(:2ZR2Zs tvcc5v0-host-regulatorregulator-fixed  qQdefault_ vcc5v0_hosts vcc-sysregulator-fixedvcc_sys(:LK@RLK@ svdd-logpwm-regulator avdd_log(: 5R\s compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4cpudevice_typeregenable-methodclocks#cooling-cellsdynamic-power-coefficientoperating-points-v2cpu-supplyphandleportsinterruptsarm,no-tick-in-suspendclock-frequencyclock-output-names#clock-cellsranges#dma-cellsclock-namesreg-names#interrupt-cellsaspm-no-l0sbus-rangeinterrupt-namesinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapphysphy-namesresetsreset-namesstatusep-gpiosnum-lanespinctrl-namespinctrl-0interrupt-controllerpower-domainsrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaymax-frequencyfifo-depthassigned-clock-ratesbus-widthcap-mmc-highspeedcap-sd-highspeedcd-gpiosdisable-wparasan,soc-ctl-sysconmmc-hs400-1_8vmmc-hs400-enhanced-strobenon-removabledr_modephy_typesnps,dis_enblslpm_quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirk#sound-dai-cellsremote-endpointmsi-controlleraffinity#io-channel-cellsvref-supplyi2c-scl-rising-time-nsi2c-scl-falling-time-nsrealtek,in1-differentialreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#power-domain-cellspm_qospmu1830-supplyrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvddio-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-off-in-suspendregulator-on-in-suspendregulator-suspend-microvoltfcs,suspend-voltage-selectorvin-supply#pwm-cells#iommu-cells#reset-cellsbt656-supplyaudio-supplysdmmc-supplygpio1830-supply#phy-cellsdmasdma-namesrockchip,playback-channelsrockchip,capture-channelsiommusrockchip,disable-mmu-resetsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namesound-daiddc-i2c-busrockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowrockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsstdout-pathenable-gpiospwmsbrightness-levelsdefault-brightness-levelautorepeatdebounce-intervallabellinux,codedefault-statesimple-audio-card,widgetssimple-audio-card,routingreset-gpiosenable-active-high