8(RX:rockchip,rk3399-evbrockchip,rk3399google,rk3399evb-rev2 +!7Rockchip RK3399 Evaluation Boardaliases=/ethernet@fe300000G/i2c@ff3c0000L/i2c@ff110000Q/i2c@ff120000V/i2c@ff130000[/i2c@ff3d0000`/i2c@ff140000e/i2c@ff150000j/i2c@ff160000o/i2c@ff3e0000t/serial@ff180000|/serial@ff190000/serial@ff1a0000/serial@ff1b0000/serial@ff370000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1cpu@0cpuarm,cortex-a53arm,armv8pscidcpu@1cpuarm,cortex-a53arm,armv8pscidcpu@2cpuarm,cortex-a53arm,armv8pscidcpu@3cpuarm,cortex-a53arm,armv8pscidcpu@100cpuarm,cortex-a72arm,armv8psci cpu@101cpuarm,cortex-a72arm,armv8psci display-subsystemrockchip,display-subsystem pmu_a53arm,cortex-a53-pmu pmu_a72arm,cortex-a72-pmu psci arm,psci-1.0smctimerarm,armv8-timer@   xin24m fixed-clockn6.xin24mAamba simple-bus+Ndma-controller@ff6d0000arm,pl330arm,primecellm@ U `apb_pclkmdma-controller@ff6e0000arm,pl330arm,primecelln@ U `apb_pclkpcie@f8000000rockchip,rk3399-pcie laxi-baseapb-base+v G`aclkaclk-perfhclkpm0123syslegacyclient`     ,pcie-phy-0pcie-phy-1pcie-phy-2pcie-phy-38N8( coremgmtmgmt-stickypipepmpclkaclk disabled  (2default@interrupt-controllerJv ethernet@fe300000rockchip,rk3399-gmac0 macirq8ighfjfM`stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac_  stmmacethmokayzinputrgmii2default@  'P(dwmmc@fe3100000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshc1@@р M`biuciuciu-driveciu-sample_y reset disableddwmmc@fe3200000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshc2@Aрz(  L`biuciuciu-driveciu-sample_z reset disabledsdhci@fe330000+rockchip,rk3399-sdhci-5.1arasan,sdhci-5.13 =zN( N`clk_xinclk_ahb.emmc_cardclockA phy_arasan_okayS]llusb@fe380000 generic-ehci8`usbhostarbiterutmiusbokayusb@fe3a0000 generic-ohci:`usbhostarbiterutmiusbokayusb@fe3c0000 generic-ehci<`usbhostarbiterutmiusbokayusb@fe3e0000 generic-ohci> `usbhostarbiterutmiusbokayusb@fe800000rockchip,rk3399-dwc3+N0G`ref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clk%  usb3-otg disableddwc3 snps,dwc3iotgusb2-phyusb3-phy utmi_wide_ disabledusb@fe900000rockchip,rk3399-dwc3+N0G`ref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clk&  usb3-otg disableddwc3 snps,dwc3notgusb2-phyusb3-phy utmi_wide_ disableddp@fec00000rockchip,rk3399-cdn-dp zr(  ruo`core-clkpclkspdifgrf !_ HJ spdifdptxapbcorem: disabledportsport+endpoint@0K"|endpoint@1K#vinterrupt-controller@fee00000 arm,gic-v3v+NJP  interrupt-controller@fee20000arm,gic-v3-its[ppi-partitionsinterrupt-partition-0j interrupt-partition-1j saradc@ff100000rockchip,rk3399-saradc>sPe`saradcapb_pclk  saradc-apb disabledi2c@ff110000rockchip,rk3399-i2czA( AU `i2cpclk;2default@$+ disabledi2c@ff120000rockchip,rk3399-i2czB( BV `i2cpclk#2default@%+ disabledi2c@ff130000rockchip,rk3399-i2czC( CW `i2cpclk"2default@&+ disabledi2c@ff140000rockchip,rk3399-i2czD( DX `i2cpclk&2default@'+ disabledi2c@ff150000rockchip,rk3399-i2czE( EY `i2cpclk%2default@(+ disabledi2c@ff160000rockchip,rk3399-i2czF( FZ `i2cpclk$2default@)+ disabledserial@ff180000&rockchip,rk3399-uartsnps,dw-apb-uartQ``baudclkapb_pclkc2default@* disabledserial@ff190000&rockchip,rk3399-uartsnps,dw-apb-uartRa`baudclkapb_pclkb2default@+ disabledserial@ff1a0000&rockchip,rk3399-uartsnps,dw-apb-uartSb`baudclkapb_pclkd2default@,okayserial@ff1b0000&rockchip,rk3399-uartsnps,dw-apb-uartTc`baudclkapb_pclke2default@- disabledspi@ff1c0000(rockchip,rk3399-spirockchip,rk3066-spiG[`spiclkapb_pclkD2default@./01+ disabledspi@ff1d0000(rockchip,rk3399-spirockchip,rk3066-spiH\`spiclkapb_pclk52default@2345+ disabledspi@ff1e0000(rockchip,rk3399-spirockchip,rk3066-spiI]`spiclkapb_pclk42default@6789+ disabledspi@ff1f0000(rockchip,rk3399-spirockchip,rk3066-spiJ^`spiclkapb_pclkC2default@:;<=+ disabledspi@ff200000(rockchip,rk3399-spirockchip,rk3066-spi K_`spiclkapb_pclk2default@>?@A_+ disabledthermal-zonescpudBtripscpu_alert0ppassiveCcpu_alert1$passiveDcpu_crits criticalcooling-mapsmap0C map1DgpudBtripsgpu_alert0$passiveEgpu_crits criticalcooling-mapsmap0E tsadc@ff260000rockchip,rk3399-tsadc&azO( qOd`tsadcapb_pclk  tsadc-apbms2initdefaultsleep@FGF& disabledBqos@ffa58000syscon Oqos@ffa5c000syscon Pqos@ffa60080syscon qos@ffa60100syscon qos@ffa60180syscon qos@ffa70000syscon Sqos@ffa70080syscon Tqos@ffa74000syscon@ Qqos@ffa76000syscon` Rqos@ffa90000syscon Uqos@ffa98000syscon Hqos@ffaa0000syscon Vqos@ffaa0080syscon Wqos@ffaa8000syscon Xqos@ffaa8080syscon Yqos@ffab0000syscon Iqos@ffab0080syscon Jqos@ffab8000syscon Kqos@ffac0000syscon Lqos@ffac0080syscon Mqos@ffac8000syscon Zqos@ffac8080syscon [qos@ffad0000syscon \qos@ffad8080syscon qos@ffae0000syscon Npower-management@ff310000&rockchip,rk3399-pmusysconsimple-mfd1power-controller!rockchip,rk3399-power-controller<+pd_iep@34"PHpd_rga@33!PIJpd_vcodec@31PKpd_vdu@32 PLMpd_gpu@35#PNpd_edp@25lpd_emmc@23POpd_gmac@22fPPpd_sd@27LPQpd_sdioaudio@28PRpd_usb3@24PSTpd_vio@15+pd_hdcp@21rPUpd_isp0@19PVWpd_isp1@20PXYpd_tcpc0@RK3399_PD_TCPC0~}pd_tcpc1@RK3399_PD_TCPC1 pd_vo@16+pd_vopb@17PZ[pd_vopl@18P\syscon@ff320000)rockchip,rk3399-pmugrfsysconsimple-mfd2+jio-domains&rockchip,rk3399-pmu-io-voltage-domain disabledspi@ff350000(rockchip,rk3399-spirockchip,rk3066-spi5]]`spiclkapb_pclk<2default@^_`a+ disabledserial@ff370000&rockchip,rk3399-uartsnps,dw-apb-uart7]]"`baudclkapb_pclkf2default@b disabledi2c@ff3c0000rockchip,rk3399-i2c<z] ( ] ] `i2cpclk92default@c+ disabledi2c@ff3d0000rockchip,rk3399-i2c=z] ( ] ] `i2cpclk82default@d+ disabledi2c@ff3e0000rockchip,rk3399-i2c>z] ( ] ] `i2cpclk:2default@e+ disabledpwm@ff420000(rockchip,rk3399-pwmrockchip,rk3288-pwmBW2default@f]`pwmokaypwm@ff420010(rockchip,rk3399-pwmrockchip,rk3288-pwmBW2default@g]`pwm disabledpwm@ff420020(rockchip,rk3399-pwmrockchip,rk3288-pwmB W2default@h]`pwmokaypwm@ff420030(rockchip,rk3399-pwmrockchip,rk3288-pwmB0W2default@i]`pwmokayiommu@ff650800rockchip,iommue@svpu_mmu `aclkifaceb disablediommu@ff660480rockchip,iommu f@f@u vdec_mmu `aclkifaceb disablediommu@ff670800rockchip,iommug@*iep_mmu `aclkifaceb disabledrga@ff680000rockchip,rk3399-rgah7m`aclkhclksclkjgi  coreaxiahb_!efuse@ff690000rockchip,rk3399-efusei+} `pclk_efusecpu-id@7cpu-leakage@17gpu-leakage@18center-leakage@19cpu-leakage@1alogic-leakage@1bwafer-info@1cpmu-clock-controller@ff750000rockchip,rk3399-pmucruumjAoz]((J]clock-controller@ff760000rockchip,rk3399-cruvmAoz@BCx@(#g/;рxh<4`#Fׄׄ syscon@ff770000&rockchip,rk3399-grfsysconsimple-mfdw+io-domains"rockchip,rk3399-io-voltage-domain disabledusb2-phy@e450rockchip,rk3399-usb2phyP{`phyclkA.clk_usbphy0_480mokayhost-port| linestateokaykotg-port|0ghjotg-bvalidotg-idlinestate disabledusb2-phy@e460rockchip,rk3399-usb2phy`|`phyclkA.clk_usbphy1_480mokayhost-port| linestateokaykotg-port|0lmootg-bvalidotg-idlinestate disabledphy@f780rockchip,rk3399-emmc-phy$l`emmcclk|okaypcie-phyrockchip,rk3399-pcie-phy`refclk| phy disabledphy@ff7c0000rockchip,rk3399-typec-phy|~}`tcpdcoretcpdphy-refz~(_L uphyuphy-pipeuphy-tcphym disableddp-port| usb3-port|phy@ff800000rockchip,rk3399-typec-phy`tcpdcoretcpdphy-refz(_ M uphyuphy-pipeuphy-tcphym disableddp-port|!usb3-port|watchdog@ff848000 snps,dw-wdt|xrktimer@ff850000rockchip,rk3399-timerQhZ `pclktimerspdif@ff870000rockchip,rk3399-spdifBmtx `mclkhclkU2default@n_: disabledi2s@ff880000(rockchip,rk3399-i2srockchip,rk3066-i2sm'mmtxrx`i2s_clki2s_hclkV2default@o_: disabledi2s@ff890000(rockchip,rk3399-i2srockchip,rk3066-i2s(mmtxrx`i2s_clki2s_hclkW2default@p_: disabledi2s@ff8a0000(rockchip,rk3399-i2srockchip,rk3066-i2s)mmtxrx`i2s_clki2s_hclkX_: disabled}vop@ff8f0000rockchip,rk3399-vop-lit>wz(ׄ`aclk_vopdclk_vophclk_vopq_  axiahbdclk disabledport+ endpoint@0Krendpoint@1Ksendpoint@2Ktendpoint@3Kuendpoint@4Kv#iommu@ff8f3f00rockchip,iommu?w vopl_mmu `aclkiface_b disabledqvop@ff900000rockchip,rk3399-vop-big>vz(ׄ`aclk_vopdclk_vophclk_vopw_  axiahbdclk disabledport+ endpoint@0Kxendpoint@1Kyendpoint@2Kzendpoint@3K{endpoint@4K|"iommu@ff903f00rockchip,iommu?v vopb_mmu `aclkiface_b disabledwiommu@ff914000rockchip,iommu @P+ isp0_mmu `aclkifaceb disablediommu@ff924000rockchip,iommu @P, isp1_mmu `aclkifaceb disabledhdmi-soundsimple-audio-cardi2s hdmi-sound disabledsimple-audio-card,cpu}simple-audio-card,codec~hdmi@ff940000rockchip,rk3399-dw-hdmi(tqop`iahbisfrvpllgrfcec_m: disabled~portsport+endpoint@0Kzendpoint@1Ktmipi@ff960000*rockchip,rk3399-mipi-dsisnps,dw-mipi-dsi- po`refpclkphy_cfggrf_ apbm disabledports+port@0+endpoint@0Kyendpoint@1Krmipi@ff968000*rockchip,rk3399-mipi-dsisnps,dw-mipi-dsi. qo`refpclkphy_cfggrf_ apbm disabledports+port@0+endpoint@0K{endpoint@1Kuedp@ff970000rockchip,rk3399-edp jlo `dppclkgrf2default@_ dpm disabledports+port@0+endpoint@0Kxendpoint@1Ksgpu@ff9a0000#rockchip,rk3399-maliarm,mali-t8600 gpujobmmu_# disabledpinctrlrockchip,rk3399-pinctrlm j+Ngpio0@ff720000rockchip,gpio-bankr])Jvgpio1@ff730000rockchip,gpio-banks])Jvgpio2@ff780000rockchip,gpio-bankxP)Jvgpio3@ff788000rockchip,gpio-bankxQ)Jvgpio4@ff790000rockchip,gpio-bankyR)Jvpcfg-pull-up5pcfg-pull-downBpcfg-pull-noneQpcfg-pull-none-12maQ^ pcfg-pull-none-13maQ^ pcfg-pull-none-18maQ^pcfg-pull-none-20maQ^pcfg-pull-up-2ma5^pcfg-pull-up-8ma5^pcfg-pull-up-18ma5^pcfg-pull-up-20ma5^pcfg-pull-down-4maB^pcfg-pull-down-8maB^pcfg-pull-down-12maB^ pcfg-pull-down-18maB^pcfg-pull-down-20maB^pcfg-output-highmpcfg-output-lowyclockclk-32kedpedp-hpdgmacrgmii-pins    rmii-pins     i2c0i2c0-xfer ci2c1i2c1-xfer $i2c2i2c2-xfer %i2c3i2c3-xfer &i2c4i2c4-xfer   di2c5i2c5-xfer   'i2c6i2c6-xfer   (i2c7i2c7-xfer )i2c8i2c8-xfer ei2s0i2s0-2ch-bus`i2s0-8ch-busoi2s1i2s1-2ch-busPpsdio0sdio0-bus1sdio0-bus4@sdio0-cmdsdio0-clksdio0-cdsdio0-pwrsdio0-bkpwrsdio0-wpsdio0-intsdmmcsdmmc-bus1sdmmc-bus4@   sdmmc-clk sdmmc-cmd sdmmc-cdsdmmc-wpsleepap-pwroffddrio-pwroffspdifspdif-busnspdif-bus-1spi0spi0-clk.spi0-cs01spi0-cs1spi0-tx/spi0-rx0spi1spi1-clk 2spi1-cs0 5spi1-rx4spi1-tx3spi2spi2-clk 6spi2-cs0 9spi2-rx 8spi2-tx 7spi3spi3-clk^spi3-cs0aspi3-rx`spi3-tx_spi4spi4-clk:spi4-cs0=spi4-rx<spi4-tx;spi5spi5-clk>spi5-cs0Aspi5-rx@spi5-tx?testclktest-clkout0test-clkout1test-clkout2tsadcotp-gpioFotp-outGuart0uart0-xfer *uart0-ctsuart0-rtsuart1uart1-xfer   +uart2auart2a-xfer  uart2buart2b-xfer uart2cuart2c-xfer ,uart3uart3-xfer -uart3-ctsuart3-rtsuart4uart4-xfer buarthdcpuarthdcp-xfer pwm0pwm0-pinfpwm0-pin-pull-downvop0-pwm-pinvop1-pwm-pinpwm1pwm1-pingpwm1-pin-pull-downpwm2pwm2-pinhpwm2-pin-pull-downpwm3apwm3a-pinipwm3bpwm3b-pinhdmihdmi-i2c-xfer hdmi-cecpciepci-clkreqn-cpmpci-clkreqnb-cpmpmicpmic-int-lpmic-dvs2usb2vcc5v0-host-enbacklightpwm-backlight  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~  aexternal-gmac-clock fixed-clocksY@ .clkin_gmacAvdd-centerpwm-regulatora vdd_center 5\"okayvcc3v3-sysregulator-fixed vcc3v3_sys"2Z2Zvcc5v0-sysregulator-fixed vcc5v0_sys"LK@LK@vcc5v0-host-regulatorregulator-fixed4 2default@ vcc5v0_hostGkvcc-phy-regulatorregulator-fixedvcc_phy" compatibleinterrupt-parent#address-cells#size-cellsmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4cpudevice_typeregenable-methodclocks#cooling-cellsdynamic-power-coefficientphandleportsinterruptsarm,no-tick-in-suspendclock-frequencyclock-output-names#clock-cellsranges#dma-cellsclock-namesreg-names#interrupt-cellsaspm-no-l0sbus-rangeinterrupt-namesinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapphysphy-namesresetsreset-namesstatusep-gpiosnum-lanespinctrl-namespinctrl-0interrupt-controllerpower-domainsrockchip,grfassigned-clocksassigned-clock-parentsclock_in_outphy-supplyphy-modesnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delaymax-frequencyfifo-depthassigned-clock-ratesarasan,soc-ctl-sysconbus-widthmmc-hs400-1_8vmmc-hs400-enhanced-strobenon-removabledr_modephy_typesnps,dis_enblslpm_quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirk#sound-dai-cellsremote-endpointmsi-controlleraffinity#io-channel-cellsreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cells#power-domain-cellspm_qos#pwm-cells#iommu-cells#reset-cells#phy-cellsdmasdma-namesiommusrockchip,disable-mmu-resetsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namesound-dairockchip,pmugpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowrockchip,pinsbrightness-levelsdefault-brightness-levelenable-gpiospwmsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-onenable-active-highvin-supply