8(|X+hisilicon,hi3660-hikey960hisilicon,hi3660 + 7HiKey960psci arm,psci-0.2=smccpus+cpu-mapcluster0core0Dcore1Dcore2Dcore3Dcluster1core0Dcore1Dcore2Dcore3D cpu@0arm,cortex-a53arm,armv8HcpuTXpscif w P ncpu@1arm,cortex-a53arm,armv8HcpuTXpscif w P cpu@2arm,cortex-a53arm,armv8HcpuTXpscif w P cpu@3arm,cortex-a53arm,armv8HcpuTXpscif w P cpu@100arm,cortex-a73arm,armv8HcpuTXpscifw &cpu@101arm,cortex-a73arm,armv8HcpuTXpscifw cpu@102arm,cortex-a73arm,armv8HcpuTXpscifw cpu@103arm,cortex-a73arm,armv8HcpuTXpscifw  idle-statespscicpu-sleep-0arm,idle-state,< cluster-sleep-0arm,idle-state,@<  cpu-sleep-1arm,idle-state,&<cluster-sleep-1arm,idle-state , T< l2-cache0cache l2-cache1cacheopp_table0operating-points-v2Mopp00X@_ `mopp01X;_ 5mopp02XSҀ_ mopp03XeE@_B@mopp04Xm5_mopp_table1operating-points-v2Mopp10X5ү_ `mopp11XT@_ 5mopp12Xk@_ mopp13X}_B@mopp14XB_minterrupt-controller@e82b0000 arm,gic-400@T++ +@ +` ~  a53-pmuarm,cortex-a53-pmu0a73-pmuarm,cortex-a73-pmu0 timerarm,armv8-timer 0   soc simple-bus+crg_ctrl@fff35000 hisilicon,hi3660-crgctrlsysconTPcrg_rst_controllerhisilicon,hi3660-resetpctrl@e8a09000hisilicon,hi3660-pctrlsysconT蠐 crg_ctrl@fff34000 hisilicon,hi3660-pmuctrlsysconT@sctrl@fff0a000hisilicon,hi3660-sctrlsysconT4iomcu@ffd7e000hisilicon,hi3660-iomcusysconTresethisilicon,hi3660-resetmailbox@e896b000hisilicon,hi3660-mboxT薰stub_clock@e896b500hisilicon,hi3660-stub-clkT薵  timer@fff14000arm,sp804arm,primecellT@01   timer1timer2apb_pclki2c@ffd71000snps,designware-i2cT v+ " )default7AokayHLS-I2C0i2c@ffd72000snps,designware-i2cT  w+ " )default7Aokayadv7533@39Aok adi,adv7533T9i2c@fdf0c000snps,designware-i2cT Q+7 "x)default7 Adisabledi2c@fdf0b000snps,designware-i2cT :+6 "`)default7AokayHLS-I2C1serial@fdf02000arm,pl011arm,primecellT  Jhuartclkapb_pclk)default7 ! Adisabledserial@fdf00000arm,pl011arm,primecellT K99uartclkapb_pclk)default7"# Adisabledserial@fdf03000arm,pl011arm,primecellT0 L:uartclkapb_pclk)default7$% Adisabledserial@ffd74000arm,pl011arm,primecellT@ ruartclkapb_pclk)default7&'Aokay HLS-UART0serial@fdf01000arm,pl011arm,primecellT M;;uartclkapb_pclk)default7()Aokaybluetooth ti,wl1837-st N*[-serial@fdf05000arm,pl011arm,primecellTP N<<uartclkapb_pclk)default7+, Adisabledserial@fff32000arm,pl011arm,primecellT  O uartclkapb_pclk)default7-.Aokay HLS-UART1dma@fdf30000hisilicon,k3-dma-1.0Tep}  > hi3660_dmartc@fff04000arm,pl031arm,primecellT@ . apb_pclkgpio@e8a0b000arm,pl061arm,primecellT蠰 T/~ apb_pclkLTP901[PMU0_SSI][PMU1_SSI][PMU2_SSI][PMU0_CLKOUT][JTAG_TCK][JTAG_TMS]gpio@e8a0c000arm,pl061arm,primecellT U/~  apb_pclkC[JTAG_TRST_N][JTAG_TDI][JTAG_TDO]NCNC[I2C3_SCL][I2C3_SDA]NCgpio@e8a0d000arm,pl061arm,primecellT V/~! apb_pclkGNCNCNCGPIO-JGPIO_020_HDMI_SELGPIO-LGPIO_022_UFSBUCK_INT_NGPIO-Ggpio@e8a0e000arm,pl061arm,primecellT W/~" apb_pclkJ[CSI0_MCLK][CSI1_MCLK]NC[I2C2_SCL][I2C2_SDA][I2C3_SCL][I2C3_SDA]NCgpio@e8a0f000arm,pl061arm,primecellT X/~# apb_pclkANCNCPWR_BTN_NGPIO_035_PMU2_ENGPIO_036_USB_HUB_RESETNCNCNCJgpio@e8a10000arm,pl061arm,primecellT Y/&~$ apb_pclkQGPIO-HGPIO_041_HDMI_PDTP904TP905NCNCGPIO_046_HUB_VDD33_ENGPIO_047_PMU1_ENgpio@e8a11000arm,pl061arm,primecellT Z/.~% apb_pclkANCNCNCGPIO_051_WIFI_ENGPIO-I[SD_DAT1][SD_DAT2][UART1_RXD]Lgpio@e8a12000arm,pl061arm,primecellT  [/6~& apb_pclky[UART1_TXD][UART0_CTS][UART0_RTS][UART0_RXD][UART0_TXD][SOC_BT_UART4_CTS_N][SOC_BT_UART4_RTS_N][SOC_BT_UART4_RXD]gpio@e8a13000arm,pl061arm,primecellT0 \/>~' apb_pclk?[SOC_BT_UART4_TXD]NC[PMU_HKADC_SSI]NCGPIO_068_SELNCNCNCgpio@e8a14000arm,pl061arm,primecellT@ ]/F~( apb_pclkNCNCNCGPIO-KNCNCNCNCgpio@e8a15000arm,pl061arm,primecellTP ^/N~) apb_pclkNCNCNCNCNCNCNCNCgpio@e8a16000arm,pl061arm,primecellT` _/V~* apb_pclk$NC[PCIE_PERST_N]NCNCNCNCNCNC9gpio@e8a17000arm,pl061arm,primecellTp ` /^/e~+ apb_pclkNCNCNCNCgpio@e8a18000arm,pl061arm,primecellT血 a/f~, apb_pclkNCNCNCNCNCNCNCNCgpio@e8a19000arm,pl061arm,primecellT衐 b/n~- apb_pclkNCNCNCNCNCNCNCNCgpio@e8a1a000arm,pl061arm,primecellT衠 c/v~. apb_pclk'NCNCNCNCNCNCGPIO_126_BT_ENTP902*gpio@e8a1b000arm,pl061arm,primecellT衰 d~/ apb_pclkgpio@e8a1c000arm,pl061arm,primecellT e~0 apb_pclkgpio@ff3b4000arm,pl061arm,primecellT;@ f0~1 apb_pclkm[UFS_REF_CLK][UFS_RST_N][SPI1_SCLK][SPI1_DIN][SPI1_DOUT][SPI1_CS]GPIO_150_USER_LED1GPIO_151_USER_LED28gpio@ff3b5000arm,pl061arm,primecellT;P g0~2 apb_pclkNCNCNCNCgpio@e8a1f000arm,pl061arm,primecellT h1~3 apb_pclk@[SD_CLK][SD_CMD][SD_DATA0][SD_DATA1][SD_DATA2][SD_DATA3]gpio@e8a20000arm,pl061arm,primecellT i~24 apb_pclk^[WL_SDIO_CLK][WL_SDIO_CMD][WL_SDIO_DATA0][WL_SDIO_DATA1][WL_SDIO_DATA2][WL_SDIO_DATA3]gpio@fff0b000arm,pl061arm,primecellT j3~4 apb_pclkd[GPIO_176_PMU_PWR_HOLD]NA[SYSCLK_EN]GPIO_179_WL_WAKEUP_APGPIO_180_HDMI_INTNAGPIO-F[I2C0_SCL]Dgpio@fff0c000arm,pl061arm,primecellT k3~4 apb_pclk^[I2C0_SDA][I2C1_SCL][I2C1_SDA][I2C1_SCL][I2C1_SDA]GPIO_189_USER_LED3GPIO_190_USER_LED4Kgpio@fff0d000arm,pl061arm,primecellT l3 ~4 apb_pclkt[PCM_DI][PCM_DO][PCM_CLK][PCM_FS][GPIO_196_I2S2_DI][GPIO_197_I2S2_DO][GPIO_198_I2S2_XCLK][GPIO_199_I2S2_XFS]gpio@fff0e000arm,pl061arm,primecellT m 33~4 apb_pclkzNCNCGPIO_202_VBUS_TYPECGPIO_203_SD_DETGPIO_204_PMU12_IRQ_NGPIO_205_WIFI_ACTIVEGPIO_206_USBSW_SELGPIO_207_BT_ACTIVE:gpio@fff0f000arm,pl061arm,primecellT n3~4 apb_pclkLGPIO-AGPIO-BGPIO-CGPIO-DGPIO-E[PCIE_CLKREQ_N][PCIE_WAKE_N][SPI0_CLK]gpio@fff10000arm,pl061arm,primecellT o3$~4 apb_pclkB[SPI0_DIN][SPI0_DOUT][SPI0_CS]GPIO_219_CC_INTNCNC[PMU_INT]6gpio@fff1d000arm,pl061arm,primecellT ~4 apb_pclkspi@ffd68000arm,pl022arm,primecellTր+ t apb_pclk)default75 6AokayHLS-SPI0spi@ff3b3000arm,pl022arm,primecellT;0+ 85 apb_pclk)default77 8AokayHHS-SPI1pcie@f4000000hisilicon,kirin960-pcie@T? dbiapbphyconfig+Hpci~ msi!4(RSQP:pcie_phy_refpcie_auxpcie_apb_phypcie_apb_syspcie_aclk B9ufs@ff3b0000#hisilicon,hi3660-ufsjedec,ufs-1.1 T;;  feref_clkphy_clkN " \rstdwmmc1@ff37f000hisilicon,hi3660-dw-mshcT7+ Kciubiu0 "\reseth4Aokay :)default 7;<=>?dwmmc2@ff3ff000hisilicon,hi3660-dw-mshcT?+ Lciubiu "\resetAok-7)default 7@ABCwlcore@2 ti,wl1837T Dwatchdog@e8a06000arm,sp805-wdtarm,primecellT` ,  apb_pclkwatchdog@e8a07000arm,sp805-wdtarm,primecellTp -  apb_pclktsensor@fff30000hisilicon,hi3660-tsensorT JEthermal-zonescls0`ndEtripstrip-point@0Opassivetrip-point@1$OpassiveFcooling-mapsmap0F map1F gpio-rangeGpinmux@e896c000pinctrl-singleT > [GGt/pmu_pmx_func u csi0_pwd_n_pmx_funcuDcsi1_pwd_n_pmx_funcuLisp0_pmx_funcuXdhisp1_pmx_funcu\lppwr_key_pmx_funcuHi2c3_pmx_funcu,0i2c4_pmx_funcupcie_perstn_pmx_funcu\usbhub5734_pmx_funcu uart0_pmx_funcu uart1_pmx_func u"uart2_pmx_func u$uart3_pmx_func u&uart4_pmx_func u(uart5_pmx_func u+uart6_pmx_func u-cam0_rst_pmx_funcucam1_rst_pmx_funcu$pinmux@ff37e000pinctrl-singleT7 >[G1sd_pmx_func0u ;pinmux@ff3b6000pinctrl-singleT;`0 >[G 0ufs_pmx_funcuspi3_pmx_func u 7pinmux@ff3fd000pinctrl-singleT? >[G2sdio_pmx_func0u @pinmux@fff11000pinctrl-singleT >[G*3i2s2_pmx_func uDHLPslimbus_pmx_funcu,0i2c0_pmx_funcui2c1_pmx_funcu i2c7_pmx_funcu$(pcie_pmx_funcuspi2_pmx_func u5i2s0_pmx_func u48<@pinmux@e896c800pinconf-singleT pmu_cfg_func u  i2c3_cfg_funcu8<csi0_pwd_n_cfg_funcuPcsi1_pwd_n_cfg_funcuXisp0_cfg_funcudptisp1_cfg_funcuhx|pwr_key_cfg_funcuIuart1_cfg_func u#uart2_cfg_func u%uart5_cfg_func u,cam0_rst_cfg_funcuuart0_cfg_funcu!uart6_cfg_func u.uart3_cfg_func u'uart4_cfg_func u)cam1_rst_cfg_funcu0pinmux@ff3b6800pinconf-singleT;h ufs_cfg_funcu0spi3_cfg_funcupinmux@ff3fd800pinconf-singleT? sdio_clk_cfg_funcuAsdio_cfg_func(u Bpinmux@ff37e800pinconf-singleT7 sd_clk_cfg_funcu<sd_cfg_func(u =pinmux@fff11800pinconf-singleT i2c0_cfg_funcu i2c1_cfg_funcu$(i2c7_cfg_funcu,0slimbus_cfg_funcu48i2s0_cfg_func u@DHLi2s2_cfg_func uPTX\pcie_cfg_funcuspi2_cfg_func uusb_cfg_funcualiases/soc/dwmmc1@ff37f000/soc/dwmmc2@ff3ff000/soc/serial@fdf02000/soc/serial@fdf00000/soc/serial@fdf03000/soc/serial@ffd74000 /soc/serial@fdf01000/soc/serial@fdf05000/soc/serial@fff32000chosen#serial6:115200n8memory@0HmemoryTreserved-memory+ramoops@32000000ramoopsT2/;Hreboot-mode-syscon@32100000sysconsimple-mfdT2reboot-modesyscon-reboot-modeT[wfUgwfUwwfUkeys gpio-keys)default7HIpower UJ HGPIO Powertleds gpio-ledsuser_led1 Huser_led1 U8 heartbeatuser_led2 Huser_led2 U8mmc0user_led3 Huser_led3 UKoffuser_led4 Huser_led4 UKcpu0wlan_active_led Hwifi_active U:phy0txoffbt_active_led Hbt_active U: hci0-poweroffpmic@fff34000hisilicon,hi6421v530-pmicT@~regulatorsLDO3 VOUT3_1V85w@!xLDO9VOUT9_1V8_2V952Z?LDO11VOUT11_1V8_2V952ZLDO15 VOUT15_3V0--?xLDO16 VOUT16_2V95-h>wlan-en-1-8vregulator-fixedwlan-en-regulatorw@w@ SLXpiCfirmwareopteelinaro,optee-tz=smc compatibleinterrupt-parent#address-cells#size-cellsmodelmethodcpudevice_typeregenable-methodnext-level-cachecpu-idle-statescapacity-dmips-mhzclocksoperating-points-v2#cooling-cellsdynamic-power-coefficientphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-ns#interrupt-cellsinterrupt-controllerinterruptsinterrupt-affinityranges#clock-cells#reset-cellshisi,rst-syscon#mbox-cellsmboxesclock-namesclock-frequencyresetspinctrl-namespinctrl-0statuslabelenable-gpiosmax-speed#dma-cellsdma-channelsdma-requestsdma-min-chandma-no-ccidma-typegpio-controller#gpio-cellsgpio-rangesgpio-line-namesnum-cscs-gpiosreg-namesbus-rangenum-lanesinterrupt-namesinterrupt-map-maskinterrupt-mapreset-gpiosfreq-table-hzreset-nameshisilicon,peripheral-sysconcard-detect-delaybus-widthcap-sd-highspeedsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104disable-wpcd-invertedcd-gpiosvmmc-supplyvqmmc-supplynon-removablebroken-cdcap-power-off-card#thermal-sensor-cellspolling-delaypolling-delay-passivesustainable-powerthermal-sensorstemperaturehysteresistripcontributioncooling-device#pinctrl-single,gpio-range-cells#pinctrl-cells#gpio-range-cellspinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,gpio-rangepinctrl-single,pinspinctrl-single,bias-pulldownpinctrl-single,bias-pulluppinctrl-single,drive-strengthmshc1mshc2serial0serial1serial2serial3serial4serial5serial6stdout-pathrecord-sizeconsole-sizeftrace-sizeoffsetmode-normalmode-bootloadermode-recoverywakeup-sourcelinux,codelinux,default-triggerdefault-statepanic-indicatorregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-boot-onregulator-always-ongpiostartup-delay-usenable-active-high