hC8a(ka#geniatech,xpi-3128rockchip,rk3128 +7Geniatech XPI-3128aliases=/pinctrl/gpio@2007c000C/pinctrl/gpio@20080000I/pinctrl/gpio@20084000O/pinctrl/gpio@20088000U/i2c@20072000Z/i2c@20056000_/i2c@2005a000d/i2c@2005e000i/serial@20060000q/serial@20064000y/serial@20068000/ethernet@2008c000/mmc@1021c000/mmc@10214000arm-pmuarm,cortex-a7-pmu0LMNOcpus+rockchip,rk3036-smpcpu@f00cpuarm,cortex-a7@cpu@f01cpuarm,cortex-a7cpu@f02cpuarm,cortex-a7cpu@f03cpuarm,cortex-a7opp-table-0operating-points-v2#opp-216000000.  5~~7opp-408000000.Q 5~~7opp-600000000.#F 5~~7opp-696000000.)| 57opp-816000000.0, 5g8g87Copp-1008000000.< 5OO7opp-1200000000.G 5777display-subsystemrockchip,display-subsystemO Uokayopp-table-1operating-points-v2 opp-200000000.  5opp-300000000. 5opp-400000000.ׄ 500opp-480000000.8 5timerarm,armv7-timer0   \n6oscillator fixed-clockn6xin24m*sram@10080000 mmio-sram +  smp-sram@0rockchip,rk3066-smp-sramgpu@10090000"rockchip,rk3128-maliarm,mali-400 Hgpgpmmupp0ppmmu0pp1ppmmu1 buscore x Uokay syscon@100a0000&rockchip,rk3128-pmusysconsimple-mfd power-controller!rockchip,rk3128-power-controller+ power-domain@1Ez power-domain@2(power-domain@3vop@1010e000rockchip,rk3126-vop aclk_vopdclk_vophclk_vopdef axiahbdclk Uokayport+ endpoint@00qos@1012d000rockchip,rk3128-qossyscon qos@1012e000rockchip,rk3128-qossyscon qos@1012f000rockchip,rk3128-qossyscon qos@1012f080rockchip,rk3128-qossyscon  qos@1012f100rockchip,rk3128-qossyscon qos@1012f180rockchip,rk3128-qossyscon qos@1012f200rockchip,rk3128-qossyscon interrupt-controller@10139000arm,cortex-a7-gic     $9usb@101800002rockchip,rk3128-usbrockchip,rk3066-usbsnps,dwc2 otgJotgRds@  usb2-phyUokayusb@101c0000 generic-ehci usbUokayusb@101e0000 generic-ohci usb Udisabledmmc@102140000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc!@@  Drvbiuciuciu-driveciu-sample rx-txрQresetUokaydefault&mmc@102180000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc!@  Eswbiuciuciu-driveciu-sample rx-txрRreset Udisabledmmc@1021c0000rockchip,rk3128-dw-mshcrockchip,rk3288-dw-mshc!@  Guybiuciuciu-driveciu-sample rx-txрSresetUokaydefault  !.@M&nand-controller@10500000(rockchip,rk3128-nfcrockchip,rk2928-nfcP@ Cahbnfcdefault "#$%&'() Udisabledclock-controller@20000000rockchip,rk3128-cru *xin24mS+`m}#gsyscon@20008000&rockchip,rk3128-grfsysconsimple-mfd ++usb2phy@17crockchip,rk3128-usb2phy| phyclk usb480m_phym,Uokay,host-port 5 linestateUokayotg-port$#34otg-bvalidotg-idlinestateUokayhdmi@20034000rockchip,rk3128-inno-hdmi @@ -G pclkrefdefault -./ Uokayports+port@0endpoint0port@1endpoint1Ltimer@20044000,rockchip,rk3128-timerrockchip,rk3288-timer @  aU pclktimertimer@20044020,rockchip,rk3128-timerrockchip,rk3288-timer @  aV pclktimertimer@20044040,rockchip,rk3128-timerrockchip,rk3288-timer @@  ;aW pclktimertimer@20044060,rockchip,rk3128-timerrockchip,rk3288-timer @`  <aX pclktimertimer@20044080,rockchip,rk3128-timerrockchip,rk3288-timer @  =aY pclktimertimer@200440a0,rockchip,rk3128-timerrockchip,rk3288-timer @  >aZ pclktimerwatchdog@2004c000 rockchip,rk3128-wdtsnps,dw-wdt  "? Udisabledpwm@20050000(rockchip,rk3128-pwmrockchip,rk3288-pwm ^default2 Udisabledpwm@20050010(rockchip,rk3128-pwmrockchip,rk3288-pwm ^default3UokayXpwm@20050020(rockchip,rk3128-pwmrockchip,rk3288-pwm  ^default4UokayYpwm@20050030(rockchip,rk3128-pwmrockchip,rk3288-pwm 0^default5 Udisabledi2c@20056000(rockchip,rk3128-i2crockchip,rk3288-i2c ` i2cMdefault6+ Udisabledi2c@2005a000(rockchip,rk3128-i2crockchip,rk3288-i2c  i2cNdefault7+ Udisabledi2c@2005e000(rockchip,rk3128-i2crockchip,rk3288-i2c  i2cOdefault8+ Udisabledserial@20060000&rockchip,rk3128-uartsnps,dw-apb-uart  n6MUbaudclkapb_pclktxrxdefault 9:; Udisabledserial@20064000&rockchip,rk3128-uartsnps,dw-apb-uart @ n6NVbaudclkapb_pclktxrxdefault<Uokayserial@20068000&rockchip,rk3128-uartsnps,dw-apb-uart  n6OWbaudclkapb_pclktxrxdefault= Udisabledsaradc@2006c000rockchip,saradc  [>saradcapb_pclkW saradc-apbUokayKi2c@20072000(rockchip,rk3128-i2crockchip,rk3288-i2c   i2cLdefault>+ Udisabledspi@20074000(rockchip,rk3128-spirockchip,rk3066-spi @ ARspiclkapb_pclk txrxdefault?@ABC+ Udisableddma-controller@20078000arm,pl330arm,primecell @ apb_pclk&ethernet@2008c000rockchip,rk3128-gmac @89macirqeth_wake_irq8~oMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac8 stmmacethS+1?UokayMoutputZDermiinEm|}defaultFmdiosnps,dwmac-mdio+ethernet-phy@1ethernet-phy-ieee802.3-c22yd  GdefaultHEpinctrlrockchip,rk3128-pinctrlS++gpio@2007c000rockchip,gpio-bank  $@$9HEADER_5HEADER_3HEADER_22HEADER_23HEADER_19HEADER_26HEADER_21HEADER_24HEADER_18HEADER_36HEADER_13Qgpio@20080000rockchip,gpio-bank  %A$9pHEADER_7HEADER_35HEADER_33HEADER_37HEADER_40HEADER_38HEADER_11HEADER_29HEADER_31Ugpio@20084000rockchip,gpio-bank @ &B$9:HEADER_27HEADER_8HEADER_10Ggpio@20088000rockchip,gpio-bank  'C$9;HEADER_32HEADER_12HEADER_15Mpcfg-pull-defaultJpcfg-pull-noneIemmcemmc-clkIemmc-cmdJ emmc-cmd1Jemmc-pwrJemmc-bus1Jemmc-bus4@JJJJemmc-bus8JJJJJJJJ!gmacrgmii-pinsJ J J J JJJJJJJJJJJrmii-pinsJ J JJJJJJJJFhdmihdmii2c-xfer II-hdmi-hpdI.hdmi-cecI/i2c0i2c0-xfer II>i2c1i2c1-xfer II6i2c2i2c2-xfer II7i2c3i2c3-xfer II8i2si2s-bus`I I I I IIi2s1-bus`IIIIIIlcdclcdc-dclkIlcdc-den Ilcdc-hsync Ilcdc-vsync Ilcdc-rgb24 I IIIIIIIIIIIIInfcflash-aleI"flash-cleI$flash-wrnI)flash-rdnI'flash-rdyI(flash-cs0I%flash-dqsI&flash-bus8IIIIIIII#pwm0pwm0-pinI2pwm1pwm1-pinI3pwm2pwm2-pinI4pwm3pwm3-pinI5sdiosdio-clkIsdio-cmdJsdio-pwrenJsdio-bus4@JJJJsdmmcsdmmc-clkIsdmmc-cmdJsdmmc-detJsdmmc-wpJsdmmc-pwrenJVsdmmc-bus4@JJJJspdifspdif-txIspi0spi0-clkJAspi0-cs0 JBspi0-tx J?spi0-rx J@spi0-cs1 JCspi1-clkJspi1-cs0Jspi1-txJspi1-rxJspi1-cs1Jspi2-clk Jspi2-cs0Jspi2-tx Jspi2-rx Juart0uart0-xfer JI9uart0-ctsI:uart0-rtsI;uart1uart1-xfer  J J<uart1-ctsIuart1-rts Iuart2uart2-xfer JI=uart2-ctsIuart2-rtsIdp83848cdp83848c-rstIHir-receiverir-intIPledspower-ledIRspd-led ISusb2host-drvIOmemory@60000000memory`@chosen/serial@20064000adc-keys adc-keysK&buttons72Zbutton-recovery QRecoveryWhbdc-5v-regulatorregulator-fixed|DC_5VLK@LK@Nhdmi-connnectorhdmi-connectoraportendpointL1host-pwr-5v-regulatorregulator-fixed M |HOST_PWR_5VLK@LK@NdefaultOir-receivergpio-ir-receiver MdefaultPleds gpio-ledsled-power Qpower$ondefaultRled-spd M landefaultSmcu3v3-regulatorregulator-fixed|MCU3V32Z2Zvcc-ddr-regulatorregulator-fixed|VCC_DDR``Tvcc-io-regulatorregulator-fixed|VCC_IO2Z2ZTvcc-lan-regulatorregulator-fixed|VCC_LAN2Z2ZDvcc-sd-regulatorregulator-fixed U|VCC_SD2Z2ZdefaultVvcc-sys-regulatorregulator-fixed|VCC_SYSLK@LK@NTvcc33-hdmi-regulatorregulator-fixed |VCC33_HDMI2Z2ZWvcca-33-regulatorregulator-fixed|VCCA_332Z2ZTWvdd-11-regulatorregulator-fixed|VDD_11Tvdd11-hdmi-regulatorregulator-fixed |VDD11_HDMIvdd-arm-regulatorpwm-regulator|VDD_ARM2Xa7T \vdd-log-regulatorpwm-regulator|VDD_LOG2YaBd7T\V  compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3i2c0i2c1i2c2i2c3serial0serial1serial2ethernet0mmc0mmc1interruptsinterrupt-affinityenable-methoddevice_typeregclock-latencyclocksresetsoperating-points-v2#cooling-cellscpu-supplyphandleopp-sharedopp-hzopp-microvoltopp-suspendportsstatusarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsrangesinterrupt-namesclock-namespower-domainsmali-supply#power-domain-cellspm_qosreset-namesremote-endpointinterrupt-controller#interrupt-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesvusb_a-supplyvusb_d-supplydmasdma-namesfifo-depthmax-frequencybus-widthvmmc-supplypinctrl-namespinctrl-0disable-wpcap-sd-highspeedno-mmcno-sdiocap-mmc-highspeedmmc-ddr-3_3vno-sdrockchip,grf#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parents#phy-cells#pwm-cellsreg-io-widthreg-shift#io-channel-cellsvref-supplyarm,pl330-broken-no-flushparm,pl330-periph-burst#dma-cellsrx-fifo-depthtx-fifo-depthclock_in_outphy-supplyphy-modephy-handlemax-speedreset-assert-usreset-deassert-usreset-gpiosgpio-controller#gpio-cellsgpio-line-namesbias-pull-pin-defaultbias-disablerockchip,pinsstdout-pathio-channelsio-channel-nameskeyup-threshold-microvoltlabellinux,codepress-threshold-microvoltregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onregulator-boot-ongpiostartup-delay-usvin-supplyenable-active-highfunctioncolordefault-statepwmspwm-supplypwm-dutycycle-rangeregulator-ramp-delay