8d( k,-compulab,omap3-cm-t3730ti,omap3630ti,omap3 +7CompuLab CM-T3730chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000s/ocp@68000000/serial@49042000cpus+cpu@0arm,cortex-a8{cpucpupmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus +  pinmux@30 ti,omap3-padconfpinctrl-single08+ *?]uart3-pinsznpmmc1-pins0zgreen-led-pinszdss-dpi-common-pinsz dss-dpi-cm-t35x-pins0zads7846-pinszmcspi1-pins zi2c1-pinszmcbsp2-pins z smsc1-pinszj hsusb0-pins`zrtvxz|~ twl4030-pinszAmmc2-pins0z(*,.02wl12xx-gpio-pinsz4 scm_conf@270sysconsimple-busp0+ p0pbias_regulator@2b0ti,pbias-omap3ti,pbias-omappbias_mmc_omap2430pbias_mmc_omap2430w@-clocks+clock@68 ti,clkselh+clock-mcbsp5-mux-fck@4ti,composite-mux-clockmcbsp5_mux_fck clock-mcbsp3-mux-fck@0ti,composite-mux-clockmcbsp3_mux_fck clock-mcbsp4-mux-fck@2ti,composite-mux-clockmcbsp4_mux_fck mcbsp5_fckti,composite-clock clock@4 ti,clksel+clock-mcbsp1-mux-fck@2ti,composite-mux-clockmcbsp1_mux_fck clock-mcbsp2-mux-fck@6ti,composite-mux-clockmcbsp2_mux_fck mcbsp1_fckti,composite-clock mcbsp2_fckti,composite-clockmcbsp3_fckti,composite-clockmcbsp4_fckti,composite-clockclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+ *?]twl4030-vpins-pins zdss-dpi-cm-t3730-pins0z target-module@480a6000ti,sysc-omap2ti,syscH `DH `HH `Lrevsyscsyss  ick+ H ` aes1@0 ti,omap3-aesP&  +txrxtarget-module@480c5000ti,sysc-omap2ti,syscH PDH PHH PLrevsyscsyss  ick+ H P aes2@0 ti,omap3-aesP&AB+txrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clock5Yosc_sys_ck@d40 ti,mux-clock @sys_ck@1270ti,divider-clockERp]"sys_clkout1@d70ti,gate-clock pEdpll3_x2_ckfixed-factor-clocktdpll3_m2x2_ckfixed-factor-clockt!dpll4_x2_ckfixed-factor-clock tcorex2_fckfixed-factor-clock!t#wkup_l4_ickfixed-factor-clock"tbcorex2_d3_fckfixed-factor-clock#tcorex2_d5_fckfixed-factor-clock#tclockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clock5omap_32k_fck fixed-clock5Hvirt_12m_ck fixed-clock5virt_13m_ck fixed-clock5]@virt_19200000_ck fixed-clock5$virt_26000000_ck fixed-clock5virt_38_4m_ck fixed-clock5Idpll4_ck@d00ti,omap3-dpll-per-j-type-clock"" D 0 dpll4_m2_ck@d48ti,divider-clock R? H]$dpll4_m2x2_mul_ckfixed-factor-clock$t%dpll4_m2x2_ck@d00ti,hsdiv-gate-clock%E &omap_96m_alwon_fckfixed-factor-clock&t2dpll3_ck@d00ti,omap3-dpll-core-clock"" @ 0clock@1140 ti,clksel@+clock-dpll3-m3@16ti,divider-clock dpll3_m3_ckR],clock-dpll4-m6@24ti,divider-clock dpll4_m6_ck R?]>clock-emu-src-mux@0 ti,mux-clockemu_src_mux_ck"'()vclock-pclk-fck@8ti,divider-clock pclk_fck*R]clock-pclkx2-fck@6ti,divider-clock pclkx2_fck*R]clock-atclk-fck@4ti,divider-clock atclk_fck*R]clock-traceclk-src-fck@2 ti,mux-clocktraceclk_src_fck"'()+clock-traceclk-fck@11 ti,divider-clock traceclk_fck+R]dpll3_m3x2_mul_ckfixed-factor-clock,t-dpll3_m3x2_ck@d00ti,hsdiv-gate-clock-E  .emu_core_alwon_ckfixed-factor-clock.t'sys_altclk fixed-clock55mcbsp_clks fixed-clock5core_ckfixed-factor-clockt/dpll1_fck@940ti,divider-clock/ER @]0dpll1_ck@904ti,omap3-dpll-clock"0  $ @ 4dpll1_x2_ckfixed-factor-clockt1dpll1_x2m2_ck@944ti,divider-clock1R D]Ecm_96m_fckfixed-factor-clock2t3clock@d40 ti,clksel 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sys_clkout2BR@clkout2_src_ckti,composite-clockCDBmpu_ckfixed-factor-clockEtFarm_fck@924ti,divider-clockF $Remu_mpu_alwon_ckfixed-factor-clockFt)clock@a40 ti,clksel @+clock-l3-ick@0ti,divider-clockl3_ick/R]Gclock-l4-ick@2ti,divider-clockl4_ickGR]Iclock-gpt10-mux-fck@6ti,composite-mux-clockgpt10_mux_fckH"Vclock-gpt11-mux-fck@7ti,composite-mux-clockgpt11_mux_fckH"Xclock-ssi-ssr-div-fck-3430es2@8ti,composite-divider-clockssi_ssr_div_fck_3430es2#$clock@c40 ti,clksel @+clock-rm-ick@1ti,divider-clockrm_ickIR]clock-gpt1-mux-fck@0ti,composite-mux-clock gpt1_mux_fckH"aclock-usim-mux-fck@3ti,composite-mux-clock usim_mux_fck("JKLMNOPQR]clock@a00 ti,clksel +clock-gpt10-gate-fck@11 ti,composite-gate-clockgpt10_gate_fck"Uclock-gpt11-gate-fck@12 ti,composite-gate-clockgpt11_gate_fck"Wclock-mmchs2-fck@25ti,wait-gate-clock mmchs2_fckclock-mmchs1-fck@24ti,wait-gate-clock mmchs1_fckclock-i2c3-fck@17ti,wait-gate-clock i2c3_fckclock-i2c2-fck@16ti,wait-gate-clock i2c2_fckclock-i2c1-fck@15ti,wait-gate-clock i2c1_fckclock-mcbsp5-gate-fck@10 ti,composite-gate-clockmcbsp5_gate_fck clock-mcbsp1-gate-fck@9 ti,composite-gate-clockmcbsp1_gate_fck clock-mcspi4-fck@21ti,wait-gate-clock mcspi4_fckSclock-mcspi3-fck@20ti,wait-gate-clock mcspi3_fckSclock-mcspi2-fck@19ti,wait-gate-clock mcspi2_fckSclock-mcspi1-fck@18ti,wait-gate-clock mcspi1_fckSclock-uart2-fck@14ti,wait-gate-clock uart2_fckSclock-uart1-fck@13 ti,wait-gate-clock uart1_fckSclock-hdq-fck@22ti,wait-gate-clockhdq_fckTclock-modem-fck@31ti,omap3-interface-clock modem_fck"clock-mspro-fck@23ti,wait-gate-clock mspro_fckclock-ssi-ssr-gate-fck-3430es2@0 ti,composite-no-wait-gate-clockssi_ssr_gate_fck_3430es2#~clock-mmchs3-fck@30ti,wait-gate-clock mmchs3_fckgpt10_fckti,composite-clockUVgpt11_fckti,composite-clockWXcore_96m_fckfixed-factor-clockYtcore_48m_fckfixed-factor-clock9tScore_12m_fckfixed-factor-clockZtTcore_l3_ickfixed-factor-clockGt[clock@a10 ti,clksel +clock-sdrc-ick@1ti,wait-gate-clock sdrc_ick[clock-mmchs2-ick@25ti,omap3-interface-clock mmchs2_ick\clock-mmchs1-ick@24ti,omap3-interface-clock mmchs1_ick\clock-hdq-ick@22ti,omap3-interface-clockhdq_ick\clock-mcspi4-ick@21ti,omap3-interface-clock mcspi4_ick\clock-mcspi3-ick@20ti,omap3-interface-clock mcspi3_ick\clock-mcspi2-ick@19ti,omap3-interface-clock mcspi2_ick\clock-mcspi1-ick@18ti,omap3-interface-clock mcspi1_ick\clock-i2c3-ick@17ti,omap3-interface-clock i2c3_ick\clock-i2c2-ick@16ti,omap3-interface-clock i2c2_ick\clock-i2c1-ick@15ti,omap3-interface-clock i2c1_ick\clock-uart2-ick@14ti,omap3-interface-clock uart2_ick\clock-uart1-ick@13 ti,omap3-interface-clock uart1_ick\clock-gpt11-ick@12 ti,omap3-interface-clock gpt11_ick\clock-gpt10-ick@11 ti,omap3-interface-clock gpt10_ick\clock-mcbsp5-ick@10 ti,omap3-interface-clock mcbsp5_ick\clock-mcbsp1-ick@9 ti,omap3-interface-clock mcbsp1_ick\clock-omapctrl-ick@6ti,omap3-interface-clock omapctrl_ick\clock-aes2-ick@28ti,omap3-interface-clock aes2_ick\clock-sha12-ick@27ti,omap3-interface-clock sha12_ick\clock-icr-ick@29ti,omap3-interface-clockicr_ick\clock-des2-ick@26ti,omap3-interface-clock des2_ick\clock-mspro-ick@23ti,omap3-interface-clock mspro_ick\clock-mailboxes-ick@7ti,omap3-interface-clockmailboxes_ick\clock-sad2d-ick@3ti,omap3-interface-clock sad2d_ickGclock-hsotgusb-ick-3430es2@4"ti,omap3-hsotgusb-interface-clockhsotgusb_ick_3430es2[clock-ssi-ick-3430es2@0ti,omap3-ssi-interface-clockssi_ick_3430es2]clock-mmchs3-ick@30ti,omap3-interface-clock mmchs3_ick\gpmc_fckfixed-factor-clock[tcore_l4_ickfixed-factor-clockIt\clock@e00 ti,clksel+clock-dss-tv-fckti,gate-clock dss_tv_fckAEclock-dss-96m-fckti,gate-clock dss_96m_fckYEclock-dss2-alwon-fckti,gate-clockdss2_alwon_fck"Eclock-dss1-alwon-fck-3430es2@0ti,dss-gate-clockdss1_alwon_fck_3430es2^dummy_ck fixed-clock5clock@c00 ti,clksel +clock-gpt1-gate-fck@0ti,composite-gate-clockgpt1_gate_fck"`clock-gpio1-dbck@3ti,gate-clock gpio1_dbck_clock-wdt2-fck@5ti,wait-gate-clock wdt2_fck_clock-sr1-fck@6ti,wait-gate-clocksr1_fck"clock-sr2-fck@7ti,wait-gate-clocksr2_fck"clock-usim-gate-fck@9 ti,composite-gate-clockusim_gate_fckYgpt1_fckti,composite-clock`awkup_32k_fckfixed-factor-clockHt_clock@c10 ti,clksel +clock-wdt2-ick@5ti,omap3-interface-clock wdt2_ickbclock-wdt1-ick@4ti,omap3-interface-clock wdt1_ickbclock-gpio1-ick@3ti,omap3-interface-clock gpio1_ickbclock-omap-32ksync-ick@2ti,omap3-interface-clockomap_32ksync_ickbclock-gpt12-ick@1ti,omap3-interface-clock gpt12_ickbclock-gpt1-ick@0ti,omap3-interface-clock gpt1_ickbclock-usim-ick@9 ti,omap3-interface-clock usim_ickbper_96m_fckfixed-factor-clock2t per_48m_fckfixed-factor-clock9tcclock@1000 ti,clksel+clock-uart3-fck@11 ti,wait-gate-clock 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ti,clksel@+clock-gpt2-mux-fck@0ti,composite-mux-clock gpt2_mux_fckH"fclock-gpt3-mux-fck@1ti,composite-mux-clock gpt3_mux_fckH"hclock-gpt4-mux-fck@2ti,composite-mux-clock gpt4_mux_fckH"jclock-gpt5-mux-fck@3ti,composite-mux-clock gpt5_mux_fckH"lclock-gpt6-mux-fck@4ti,composite-mux-clock gpt6_mux_fckH"nclock-gpt7-mux-fck@5ti,composite-mux-clock gpt7_mux_fckH"pclock-gpt8-mux-fck@6ti,composite-mux-clock gpt8_mux_fckH"rclock-gpt9-mux-fck@7ti,composite-mux-clock gpt9_mux_fckH"tgpt2_fckti,composite-clockefgpt3_fckti,composite-clockghgpt4_fckti,composite-clockijgpt5_fckti,composite-clockklgpt6_fckti,composite-clockmngpt7_fckti,composite-clockopgpt8_fckti,composite-clockqrgpt9_fckti,composite-clockstper_32k_alwon_fckfixed-factor-clockHtdper_l4_ickfixed-factor-clockItuclock@1010 ti,clksel+clock-gpio6-ick@17ti,omap3-interface-clock gpio6_ickuclock-gpio5-ick@16ti,omap3-interface-clock gpio5_ickuclock-gpio4-ick@15ti,omap3-interface-clock gpio4_ickuclock-gpio3-ick@14ti,omap3-interface-clock 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environment&partition@2a0000linux*@partition@6a0000rootfsjethernet@gpmcsmsc,lan9221smsc,lan91152Tbt(--8IxKKlZ   - :default    target-module@480ab000ti,sysc-omap2ti,syscH H H revsyscsyss *  fck+ H usb@0ti,omap3-musb\]#mcdma P [ c default  l {   usb2-phy0 2dss@48050000 ti,omap3-dssHokay dss_corefck+default dispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H protophypll disabled dss_dsi1 fcksys_clk+encoder@48050800ti,omap3-rfbiH disabled dss_rfbifckickencoder@48050c00ti,omap3-vencH okay dss_vencfcktv_dac_clk portendpoint  ssi-controller@48058000 ti,omap3-ssissiokayHHsysgddG#gdd_mpu+  ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portHHtxrxCDssi-port@4805b000ti,omap3-ssi-portHHtxrxEFserial@49042000ti,omap3-uartI P&QR+txrxuart45lregulator-abb-mpu ti,abb-v1 abb_mpu_iva+H0rH0hbase-addressint-address "  ` sO7pinmux@480025a0 ti,omap3-padconfpinctrl-singleH%\+ *?]isp@480bc000 ti,omap3-ispH H   ports+bandgap@48002524H%$ti,omap36xx-bandgap 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