8( `2logicpd,dm3730-som-lv-devkitti,omap3630ti,omap3 ++7LogicPD Zoom DM3730 SOM-LV Development Kitchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000s/ocp@68000000/serial@49042000 {/displaycpus+cpu@0arm,cortex-a8cpucpupmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush + l3_mainl4@48000000ti,omap3-l4-coresimple-bus+  Hscm@2000ti,omap3-scmsimple-bus +  pinmux@30 ti,omap3-padconfpinctrl-single08+"3Hfmm3-pins0468:mcbsp2-pins  uart2-pins(DFHJhmcspi1-pins hsusb2-pins0       hsusb-otg-pins`rtvxz|~i2c1-pinsi2c2-pinsi2c3-pinstsc2004-pinsVtwl4030-pinsAgpio-key-pins"led-pins.$lan9221-pinsT mmc1-pins@lcd-enable-pinsZ&dss-dpi1-pinsscm_conf@270sysconsimple-busp0+  p0pbias_regulator@2b0ti,pbias-omap3ti,pbias-omappbias_mmc_omap2430pbias_mmc_omap2430w@-clocks+clock@68 ti,clkselh+clock-mcbsp5-mux-fck@4ti,composite-mux-clockmcbsp5_mux_fck clock-mcbsp3-mux-fck@0ti,composite-mux-clockmcbsp3_mux_fck clock-mcbsp4-mux-fck@2ti,composite-mux-clockmcbsp4_mux_fck mcbsp5_fckti,composite-clock clock@4 ti,clksel+clock-mcbsp1-mux-fck@2ti,composite-mux-clockmcbsp1_mux_fck clock-mcbsp2-mux-fck@6ti,composite-mux-clockmcbsp2_mux_fck mcbsp1_fckti,composite-clock mcbsp2_fckti,composite-clockmcbsp3_fckti,composite-clockmcbsp4_fckti,composite-clockclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+"3Hfhsusb1-reset-pins!wl127x-gpio-pins  twl4030-vpins-pins led-wkup-pins$%backlight-pins)target-module@480a6000ti,sysc-omap2ti,syscH `DH `HH `Lrevsyscsyss "ick+  H ` aes1@0 ti,omap3-aesP/  4txrxtarget-module@480c5000ti,sysc-omap2ti,syscH PDH PHH PLrevsyscsyss "ick+  H P aes2@0 ti,omap3-aesP/AB4txrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clock>Yosc_sys_ck@d40 ti,mux-clock @sys_ck@1270ti,divider-clockN[pf"sys_clkout1@d70ti,gate-clock pNdpll3_x2_ckfixed-factor-clock}dpll3_m2x2_ckfixed-factor-clock}!dpll4_x2_ckfixed-factor-clock }corex2_fckfixed-factor-clock!}#wkup_l4_ickfixed-factor-clock"}bcorex2_d3_fckfixed-factor-clock#}corex2_d5_fckfixed-factor-clock#}clockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clock>omap_32k_fck fixed-clock>Hvirt_12m_ck fixed-clock>virt_13m_ck fixed-clock>]@virt_19200000_ck fixed-clock>$virt_26000000_ck fixed-clock>virt_38_4m_ck fixed-clock>Idpll4_ck@d00ti,omap3-dpll-per-j-type-clock"" D 0 dpll4_m2_ck@d48ti,divider-clock [? Hf$dpll4_m2x2_mul_ckfixed-factor-clock$}%dpll4_m2x2_ck@d00ti,hsdiv-gate-clock%N &omap_96m_alwon_fckfixed-factor-clock&}2dpll3_ck@d00ti,omap3-dpll-core-clock"" @ 0clock@1140 ti,clksel@+clock-dpll3-m3@16ti,divider-clock dpll3_m3_ck[f,clock-dpll4-m6@24ti,divider-clock dpll4_m6_ck [?f>clock-emu-src-mux@0 ti,mux-clockemu_src_mux_ck"'()vclock-pclk-fck@8ti,divider-clock pclk_fck*[fclock-pclkx2-fck@6ti,divider-clock pclkx2_fck*[fclock-atclk-fck@4ti,divider-clock atclk_fck*[fclock-traceclk-src-fck@2 ti,mux-clocktraceclk_src_fck"'()+clock-traceclk-fck@11 ti,divider-clock traceclk_fck+[fdpll3_m3x2_mul_ckfixed-factor-clock,}-dpll3_m3x2_ck@d00ti,hsdiv-gate-clock-N  .emu_core_alwon_ckfixed-factor-clock.}'sys_altclk fixed-clock>5mcbsp_clks fixed-clock>core_ckfixed-factor-clock}/dpll1_fck@940ti,divider-clock/N[ @f0dpll1_ck@904ti,omap3-dpll-clock"0  $ @ 4dpll1_x2_ckfixed-factor-clock}1dpll1_x2m2_ck@944ti,divider-clock1[ DfEcm_96m_fckfixed-factor-clock2}3clock@d40 ti,clksel @+clock-dpll3-m2@27ti,divider-clock dpll3_m2_ck[fclock-omap-96m-fck@6 ti,mux-clock omap_96m_fck3"Yclock-omap-54m-fck@5 ti,mux-clock omap_54m_fck45Aclock-omap-48m-fck@3 ti,mux-clock omap_48m_fck659clock@e40 ti,clksel@+clock-dpll4-m3@8ti,divider-clock dpll4_m3_ck [ f7clock-dpll4-m4@0ti,divider-clock dpll4_m4_ck [f:dpll4_m3x2_mul_ckfixed-factor-clock7}8dpll4_m3x2_ck@d00ti,hsdiv-gate-clock8N 4cm_96m_d2_fckfixed-factor-clock3}6omap_12m_fckfixed-factor-clock9}Zdpll4_m4x2_mul_ckti,fixed-factor-clock:;dpll4_m4x2_ck@d00ti,gate-clock;N ^dpll4_m5_ck@f40ti,divider-clock [?@f<dpll4_m5x2_mul_ckti,fixed-factor-clock<=dpll4_m5x2_ck@d00ti,hsdiv-gate-clock=N zdpll4_m6x2_mul_ckfixed-factor-clock>}?dpll4_m6x2_ck@d00ti,hsdiv-gate-clock?N @emu_per_alwon_ckfixed-factor-clock@}(clock@d70 ti,clksel p+clock-clkout2-src-gate@7 ti,composite-no-wait-gate-clockclkout2_src_gate_ck/Cclock-clkout2-src-mux@0ti,composite-mux-clockclkout2_src_mux_ck/"3ADclock-sys-clkout2@3ti,divider-clock sys_clkout2B[@clkout2_src_ckti,composite-clockCDBmpu_ckfixed-factor-clockE}Farm_fck@924ti,divider-clockF $[emu_mpu_alwon_ckfixed-factor-clockF})clock@a40 ti,clksel @+clock-l3-ick@0ti,divider-clockl3_ick/[fGclock-l4-ick@2ti,divider-clockl4_ickG[fIclock-gpt10-mux-fck@6ti,composite-mux-clockgpt10_mux_fckH"Vclock-gpt11-mux-fck@7ti,composite-mux-clockgpt11_mux_fckH"Xclock-ssi-ssr-div-fck-3430es2@8ti,composite-divider-clockssi_ssr_div_fck_3430es2#$clock@c40 ti,clksel @+clock-rm-ick@1ti,divider-clockrm_ickI[fclock-gpt1-mux-fck@0ti,composite-mux-clock gpt1_mux_fckH"aclock-usim-mux-fck@3ti,composite-mux-clock usim_mux_fck("JKLMNOPQRfclock@a00 ti,clksel +clock-gpt10-gate-fck@11 ti,composite-gate-clockgpt10_gate_fck"Uclock-gpt11-gate-fck@12 ti,composite-gate-clockgpt11_gate_fck"Wclock-mmchs2-fck@25ti,wait-gate-clock mmchs2_fckclock-mmchs1-fck@24ti,wait-gate-clock mmchs1_fckclock-i2c3-fck@17ti,wait-gate-clock i2c3_fckclock-i2c2-fck@16ti,wait-gate-clock i2c2_fckclock-i2c1-fck@15ti,wait-gate-clock i2c1_fckclock-mcbsp5-gate-fck@10 ti,composite-gate-clockmcbsp5_gate_fck clock-mcbsp1-gate-fck@9 ti,composite-gate-clockmcbsp1_gate_fck clock-mcspi4-fck@21ti,wait-gate-clock mcspi4_fckSclock-mcspi3-fck@20ti,wait-gate-clock mcspi3_fckSclock-mcspi2-fck@19ti,wait-gate-clock mcspi2_fckSclock-mcspi1-fck@18ti,wait-gate-clock mcspi1_fckSclock-uart2-fck@14ti,wait-gate-clock uart2_fckSclock-uart1-fck@13 ti,wait-gate-clock uart1_fckSclock-hdq-fck@22ti,wait-gate-clockhdq_fckTclock-modem-fck@31ti,omap3-interface-clock modem_fck"clock-mspro-fck@23ti,wait-gate-clock mspro_fckclock-ssi-ssr-gate-fck-3430es2@0 ti,composite-no-wait-gate-clockssi_ssr_gate_fck_3430es2#~clock-mmchs3-fck@30ti,wait-gate-clock mmchs3_fckgpt10_fckti,composite-clockUVgpt11_fckti,composite-clockWXcore_96m_fckfixed-factor-clockY}core_48m_fckfixed-factor-clock9}Score_12m_fckfixed-factor-clockZ}Tcore_l3_ickfixed-factor-clockG}[clock@a10 ti,clksel +clock-sdrc-ick@1ti,wait-gate-clock sdrc_ick[clock-mmchs2-ick@25ti,omap3-interface-clock mmchs2_ick\clock-mmchs1-ick@24ti,omap3-interface-clock mmchs1_ick\clock-hdq-ick@22ti,omap3-interface-clockhdq_ick\clock-mcspi4-ick@21ti,omap3-interface-clock mcspi4_ick\clock-mcspi3-ick@20ti,omap3-interface-clock mcspi3_ick\clock-mcspi2-ick@19ti,omap3-interface-clock mcspi2_ick\clock-mcspi1-ick@18ti,omap3-interface-clock mcspi1_ick\clock-i2c3-ick@17ti,omap3-interface-clock i2c3_ick\clock-i2c2-ick@16ti,omap3-interface-clock i2c2_ick\clock-i2c1-ick@15ti,omap3-interface-clock i2c1_ick\clock-uart2-ick@14ti,omap3-interface-clock uart2_ick\clock-uart1-ick@13 ti,omap3-interface-clock uart1_ick\clock-gpt11-ick@12 ti,omap3-interface-clock gpt11_ick\clock-gpt10-ick@11 ti,omap3-interface-clock gpt10_ick\clock-mcbsp5-ick@10 ti,omap3-interface-clock mcbsp5_ick\clock-mcbsp1-ick@9 ti,omap3-interface-clock mcbsp1_ick\clock-omapctrl-ick@6ti,omap3-interface-clock omapctrl_ick\clock-aes2-ick@28ti,omap3-interface-clock aes2_ick\clock-sha12-ick@27ti,omap3-interface-clock sha12_ick\clock-icr-ick@29ti,omap3-interface-clockicr_ick\clock-des2-ick@26ti,omap3-interface-clock des2_ick\clock-mspro-ick@23ti,omap3-interface-clock mspro_ick\clock-mailboxes-ick@7ti,omap3-interface-clockmailboxes_ick\clock-sad2d-ick@3ti,omap3-interface-clock sad2d_ickGclock-hsotgusb-ick-3430es2@4"ti,omap3-hsotgusb-interface-clockhsotgusb_ick_3430es2[clock-ssi-ick-3430es2@0ti,omap3-ssi-interface-clockssi_ick_3430es2]clock-mmchs3-ick@30ti,omap3-interface-clock mmchs3_ick\gpmc_fckfixed-factor-clock[}core_l4_ickfixed-factor-clockI}\clock@e00 ti,clksel+clock-dss-tv-fckti,gate-clock dss_tv_fckANclock-dss-96m-fckti,gate-clock dss_96m_fckYNclock-dss2-alwon-fckti,gate-clockdss2_alwon_fck"Nclock-dss1-alwon-fck-3430es2@0ti,dss-gate-clockdss1_alwon_fck_3430es2^dummy_ck fixed-clock>clock@c00 ti,clksel +clock-gpt1-gate-fck@0ti,composite-gate-clockgpt1_gate_fck"`clock-gpio1-dbck@3ti,gate-clock gpio1_dbck_clock-wdt2-fck@5ti,wait-gate-clock wdt2_fck_clock-sr1-fck@6ti,wait-gate-clocksr1_fck"clock-sr2-fck@7ti,wait-gate-clocksr2_fck"clock-usim-gate-fck@9 ti,composite-gate-clockusim_gate_fckYgpt1_fckti,composite-clock`awkup_32k_fckfixed-factor-clockH}_clock@c10 ti,clksel +clock-wdt2-ick@5ti,omap3-interface-clock wdt2_ickbclock-wdt1-ick@4ti,omap3-interface-clock wdt1_ickbclock-gpio1-ick@3ti,omap3-interface-clock gpio1_ickbclock-omap-32ksync-ick@2ti,omap3-interface-clockomap_32ksync_ickbclock-gpt12-ick@1ti,omap3-interface-clock gpt12_ickbclock-gpt1-ick@0ti,omap3-interface-clock gpt1_ickbclock-usim-ick@9 ti,omap3-interface-clock usim_ickbper_96m_fckfixed-factor-clock2} per_48m_fckfixed-factor-clock9}cclock@1000 ti,clksel+clock-uart3-fck@11 ti,wait-gate-clock uart3_fckcclock-gpt2-gate-fck@3ti,composite-gate-clockgpt2_gate_fck"eclock-gpt3-gate-fck@4ti,composite-gate-clockgpt3_gate_fck"gclock-gpt4-gate-fck@5ti,composite-gate-clockgpt4_gate_fck"iclock-gpt5-gate-fck@6ti,composite-gate-clockgpt5_gate_fck"kclock-gpt6-gate-fck@7ti,composite-gate-clockgpt6_gate_fck"mclock-gpt7-gate-fck@8ti,composite-gate-clockgpt7_gate_fck"oclock-gpt8-gate-fck@9 ti,composite-gate-clockgpt8_gate_fck"qclock-gpt9-gate-fck@10 ti,composite-gate-clockgpt9_gate_fck"sclock-gpio6-dbck@17ti,gate-clock gpio6_dbckdclock-gpio5-dbck@16ti,gate-clock gpio5_dbckdclock-gpio4-dbck@15ti,gate-clock gpio4_dbckdclock-gpio3-dbck@14ti,gate-clock gpio3_dbckdclock-gpio2-dbck@13 ti,gate-clock gpio2_dbckdclock-wdt3-fck@12 ti,wait-gate-clock wdt3_fckdclock-mcbsp2-gate-fck@0ti,composite-gate-clockmcbsp2_gate_fckclock-mcbsp3-gate-fck@1ti,composite-gate-clockmcbsp3_gate_fckclock-mcbsp4-gate-fck@2ti,composite-gate-clockmcbsp4_gate_fckclock-uart4-fck@18ti,wait-gate-clock uart4_fckcclock@1040 ti,clksel@+clock-gpt2-mux-fck@0ti,composite-mux-clock gpt2_mux_fckH"fclock-gpt3-mux-fck@1ti,composite-mux-clock gpt3_mux_fckH"hclock-gpt4-mux-fck@2ti,composite-mux-clock gpt4_mux_fckH"jclock-gpt5-mux-fck@3ti,composite-mux-clock gpt5_mux_fckH"lclock-gpt6-mux-fck@4ti,composite-mux-clock gpt6_mux_fckH"nclock-gpt7-mux-fck@5ti,composite-mux-clock gpt7_mux_fckH"pclock-gpt8-mux-fck@6ti,composite-mux-clock gpt8_mux_fckH"rclock-gpt9-mux-fck@7ti,composite-mux-clock gpt9_mux_fckH"tgpt2_fckti,composite-clockefgpt3_fckti,composite-clockghgpt4_fckti,composite-clockijgpt5_fckti,composite-clockklgpt6_fckti,composite-clockmngpt7_fckti,composite-clockopgpt8_fckti,composite-clockqrgpt9_fckti,composite-clockstper_32k_alwon_fckfixed-factor-clockH}dper_l4_ickfixed-factor-clockI}uclock@1010 ti,clksel+clock-gpio6-ick@17ti,omap3-interface-clock gpio6_ickuclock-gpio5-ick@16ti,omap3-interface-clock gpio5_ickuclock-gpio4-ick@15ti,omap3-interface-clock gpio4_ickuclock-gpio3-ick@14ti,omap3-interface-clock gpio3_ickuclock-gpio2-ick@13 ti,omap3-interface-clock gpio2_ickuclock-wdt3-ick@12 ti,omap3-interface-clock wdt3_ickuclock-uart3-ick@11 ti,omap3-interface-clock uart3_ickuclock-uart4-ick@18ti,omap3-interface-clock uart4_ickuclock-gpt9-ick@10 ti,omap3-interface-clock gpt9_ickuclock-gpt8-ick@9 ti,omap3-interface-clock gpt8_ickuclock-gpt7-ick@8ti,omap3-interface-clock gpt7_ickuclock-gpt6-ick@7ti,omap3-interface-clock gpt6_ickuclock-gpt5-ick@6ti,omap3-interface-clock gpt5_ickuclock-gpt4-ick@5ti,omap3-interface-clock gpt4_ickuclock-gpt3-ick@4ti,omap3-interface-clock gpt3_ickuclock-gpt2-ick@3ti,omap3-interface-clock gpt2_ickuclock-mcbsp2-ick@0ti,omap3-interface-clock mcbsp2_ickuclock-mcbsp3-ick@1ti,omap3-interface-clock mcbsp3_ickuclock-mcbsp4-ick@2ti,omap3-interface-clock mcbsp4_ickuemu_src_ckti,clkdm-gate-clockv*secure_32k_fck fixed-clock>wgpt12_fckfixed-factor-clockw} wdt1_fckfixed-factor-clockw}security_l4_ick2fixed-factor-clockI}xclock@a14 ti,clksel +clock-aes1-ick@3ti,omap3-interface-clock aes1_ickxclock-rng-ick@2ti,omap3-interface-clockrng_ickxclock-sha11-ick@1ti,omap3-interface-clock sha11_ickxclock-des1-ick@0ti,omap3-interface-clock des1_ickxclock-pka-ick@4ti,omap3-interface-clockpka_ickyclock@f00 ti,clksel+clock-cam-mclk@0ti,gate-clock cam_mclkzclock-csi2-96m-fck@1ti,gate-clock csi2_96m_fckcam_ick@f10!ti,omap3-no-wait-interface-clockINsecurity_l3_ickfixed-factor-clockG}yssi_l4_ickfixed-factor-clockI}]sr_l4_ickfixed-factor-clockI}dpll2_fck@40ti,divider-clock/N[@f{dpll2_ck@4ti,omap3-dpll-clock"{$@4 |dpll2_m2_ck@44ti,divider-clock|[Df}iva2_ck@0ti,wait-gate-clock}Nclock@a18 ti,clksel &+clock-mad2d-ick@3ti,omap3-interface-clock mad2d_ickGclock-usbtll-ick@2ti,omap3-interface-clock usbtll_ick\ssi_ssr_fck_3430es2ti,composite-clock~ssi_sst_fck_3430es2fixed-factor-clock}sys_d2_ckfixed-factor-clock"}Jomap_96m_d2_fckfixed-factor-clockY}Komap_96m_d4_fckfixed-factor-clockY}Lomap_96m_d8_fckfixed-factor-clockY}Momap_96m_d10_fckfixed-factor-clockY} Ndpll5_m2_d4_ckfixed-factor-clock}Odpll5_m2_d8_ckfixed-factor-clock}Pdpll5_m2_d16_ckfixed-factor-clock}Qdpll5_m2_d20_ckfixed-factor-clock}Rusim_fckti,composite-clockdpll5_ck@d04ti,omap3-dpll-clock""  $ L 4 dpll5_m2_ck@d50ti,divider-clock[ Pfsgx_gate_fck@b00ti,composite-gate-clock/N core_d3_ckfixed-factor-clock/}core_d4_ckfixed-factor-clock/}core_d6_ckfixed-factor-clock/}omap_192m_alwon_fckfixed-factor-clock&}core_d2_ckfixed-factor-clock/}sgx_mux_fck@b40ti,composite-mux-clock 3 @sgx_fckti,composite-clocksgx_ick@b10ti,wait-gate-clockG Ncpefuse_fck@a08ti,gate-clock" Nts_fck@a08ti,gate-clockH Nusbtll_fck@a08ti,wait-gate-clock Ndss_ick_3430es2@e10ti,omap3-dss-interface-clockINusbhost_120m_fck@1400ti,gate-clockNusbhost_48m_fck@1400ti,dss-gate-clock9Nusbhost_ick@1410ti,omap3-dss-interface-clockINclockdomainscore_l3_clkdmti,clockdomaindpll3_clkdmti,clockdomaindpll1_clkdmti,clockdomainper_clkdmti,clockdomainlemu_clkdmti,clockdomain*dpll4_clkdmti,clockdomain wkup_clkdmti,clockdomain$dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaincam_clkdmti,clockdomainiva2_clkdmti,clockdomaindpll2_clkdmti,clockdomain|d2d_clkdmti,clockdomain dpll5_clkdmti,clockdomainsgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain target-module@48320000ti,sysc-omap2ti,syscH2H2 revsysc_fckick+  H2counter@0ti,omap-counter32k interrupt-controller@48200000ti,omap3-intc3"H target-module@48056000ti,sysc-omap2ti,syscH`H`,H`(revsyscsyss# 3 "[ick+  H`dma-controller@0ti,omap3630-sdmati,omap-sdma AL Y`gpio@48310000ti,omap3-gpioH1gpio1fx3"gpio@49050000ti,omap3-gpioIgpio2x3"gpio@49052000ti,omap3-gpioI gpio3x3"gpio@49054000ti,omap3-gpioI@ gpio4x3"gpio@49056000ti,omap3-gpioI`!gpio5x3"gpio@49058000ti,omap3-gpioI"gpio6x3"serial@4806a000ti,omap3-uartH HR/124txrxuart1>lserial@4806c000ti,omap3-uartHIJ/344txrxuart2>ldefaultserial@49020000ti,omap3-uartIJ/564txrxuart3>li2c@48070000 ti,omap3-i2cH8+i2c1default>'@twl@48H fck ti,twl40303"defaultaudioti,twl4030-audiocodec rtcti,twl4030-rtc bciti,twl4030-bci  vac0 watchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1--regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3** regulator-vaux4ti,twl4030-vaux4w@w@regulator-vdd1ti,twl4030-vdd1 ' regulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0regulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5regulator-vusb1v8ti,twl4030-vusb1v8regulator-vusb3v1ti,twl4030-vusb3v1regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@regulator-vsimti,twl4030-vsimw@-gpioti,twl4030-gpiox3")twl4030-usbti,twl4030-usb 5CQ_hpwmti,twl4030-pwms*pwmledti,twl4030-pwmledspwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypad~madcti,twl4030-madcpower4ti,twl4030-power-idle-osc-offti,twl4030-power-idlei2c@48072000 ti,omap3-i2cH 9+i2c2default>i2c@48060000 ti,omap3-i2cH=+i2c3default>tsc2004@48 ti,tsc2004Hdefault !4M]@mailbox@48094000ti,omap3-mailboxmailboxH @xmbox-dsp  spi@48098000ti,omap2-mcspiH A+mcspi1@/#$%&'()* 4tx0rx0tx1rx1tx2rx2tx3rx3defaultspi@4809a000ti,omap2-mcspiH B+mcspi2 /+,-.4tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [+mcspi3 /4tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0+mcspi4/FG4tx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc1/=>4txrxSdefault  mmc@480b4000ti,omap3-hsmmcH @Vmmc2//04txrxmmc@480ad000ti,omap3-hsmmcH ^mmc3/MN4txrx^6default!+wlcore@2 ti,wl1273 /mmu@480bd400Cti,omap2-iommuH mmu_ispPmmu@5d000000Cti,omap2-iommu]mmu_iva `disabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@mpu ;< gcommontxrxwmcbsp1/ 4txrxfck `disabledtarget-module@480a0000ti,sysc-omap2ti,syscH <H @H Drevsyscsyss"ick+  H rng@0 ti,omap2-rng 4mcbsp@49022000ti,omap3-mcbspI I mpusidetone>?gcommontxrxsidetonewmcbsp2mcbsp2_sidetone/!"4txrxfckick`okaydefault#mcbsp@49024000ti,omap3-mcbspI@I mpusidetoneYZgcommontxrxsidetonewmcbsp3mcbsp3_sidetone/4txrxfckick `disabledmcbsp@49026000ti,omap3-mcbspI`mpu 67 gcommontxrxwmcbsp4/4txrxfck `disabledmcbsp@48096000ti,omap3-mcbspH `mpu QR gcommontxrxwmcbsp5/4txrxfck `disabledsham@480c3000ti,omap3-shamshamH 0d1/E4rxtarget-module@48318000ti,sysc-omap2-timerti,syscH1H1H1revsyscsyss' "fckick+  H1timer@0ti,omap3430-timerfck%Htarget-module@49032000ti,sysc-omap2-timerti,syscI I I revsyscsyss' "fckick+  I timer@0ti,omap3430-timer&timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5timer@4903a000ti,omap3430-timerI*timer6timer@4903c000ti,omap3430-timerI+timer7timer@4903e000ti,omap3430-timerI,timer8timer@49040000ti,omap3430-timerI-timer9timer@48086000ti,omap3430-timerH`.timer10timer@48088000ti,omap3430-timerH/timer11target-module@48304000ti,sysc-omap2-timerti,syscH0@H0@H0@revsyscsyss' " fckick+  H0@timer@0ti,omap3430-timer_usbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs+ default  ehci-phyohci@48064400ti,ohci-omap3HDL!ehci@48064800 ti,ehci-omapHHM9 gpmc@6e000000ti,omap3430-gpmcgpmcn/4rxtx>J+3"x0 0, nand@0,0ti,omap2-nand   \micron,mt29f4g16abbda3wkzbch8  ,,", (6)@8RIRZ(l+ethernet@gpmcdefault   smsc,lan9221smsc,lan9115*$  * $8<I6)$ lZ*  4 N ^ l ytarget-module@480ab000ti,sysc-omap2ti,syscH H H revsyscsyss 3 "fck+  H usb@0ti,omap3-musb\]gmcdma   default  9 usb2-phyc 2dss@48050000 ti,omap3-dssH`okay dss_corefck+   defaultdispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H protophypll `disabled dss_dsi1 fcksys_clk+encoder@48050800ti,omap3-rfbiH `disabled dss_rfbifckickencoder@48050c00ti,omap3-vencH  `disabled dss_vencfcktv_dac_clkportendpoint  (ssi-controller@48058000 ti,omap3-ssissi`okayHHsysgddGggdd_mpu+   ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portHHtxrxCDssi-port@4805b000ti,omap3-ssi-portHHtxrxEFserial@49042000ti,omap3-uartI P/QR4txrxuart4>lregulator-abb-mpu ti,abb-v1 abb_mpu_iva+H0rH0hbase-addressint-address " ( 9` IsO7pinmux@480025a0 ti,omap3-padconfpinctrl-singleH%\+"3Hfdefaulthsusb2-2-pins0PRT V X Z isp@480bc000 ti,omap3-ispH H  U \ports+bandgap@48002524H%$ti,omap36xx-bandgap htarget-module@480cb000ti,sysc-omap3630-srti,syscsmartreflex_coreH 8sysc fck+  H smartreflex@0ti,omap3-smartreflex-coretarget-module@480c9000ti,sysc-omap3630-srti,syscsmartreflex_mpu_ivaH 8sysc fck+  H smartreflex@480c9000ti,omap3-smartreflex-mpu-ivatarget-module@50000000ti,sysc-omap4ti,syscPP revsysc 3 fckick+  Pgpu@0#ti,omap3630-gpuimg,powervr-sgx530opp-tableoperating-points-v2-ti-cpuopp-50-300000000 ~ ssssss  opp-100-600000000 ~#F OOOOOO opp-130-800000000 ~/ 777777 opp-1000000000 ~;   opp-supplyti,omap-opp-supply thermal-zonescpu-thermal   N  tripscpu_alert 8 #passivecpu_crit _ # criticalcooling-mapsmap0 . 3memory@80000000memorywl12xx_vmmcregulator-fixedvwl1271w@w@  Bp S f hsusb2_phydefault!usb-nop-xceiv qh oscillator fixed-clock>gpio_keys gpio-keysdefault"sysboot2 }gpio3   soundti,omap-twl4030 omap3logic #leds gpio-ledsdefault$%led1 }led1  cpu0led2 }led2   nonevideo_regregulator-fixed fixed-supply2Z2Zdisplaylogicpd,type28default& ' portendpoint (backlightpwm-backlightdefault) *LK@, (2<FPZd  'regulator-vddvarioregulator-fixed vddvarioregulator-vdd33aregulator-fixedvdd33a compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2serial3display0device_typeregclocksclock-namesclock-latencyoperating-points-v2vbb-supply#cooling-cellscpu0-supplyphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsclock-output-namesreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,bit-shiftti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,dividersti,low-power-stopti,lockti,low-power-bypass#ssize-cellsti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0ti,hs_extmute_gpiobci3v1-supplyio-channelsio-channel-namesti,bb-uvoltti,bb-uampregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsti,use_poweroffvio-supplytouchscreen-fuzz-xtouchscreen-fuzz-ytouchscreen-fuzz-pressuretouchscreen-size-xtouchscreen-size-ytouchscreen-max-pressureti,x-plate-ohmsti,esd-recovery-timeout-ms#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplywp-gpioscd-gpiosvmmc-supplybus-widthcap-power-off-cardnon-removableref-clock-frequency#iommu-cellsti,#tlb-entriesstatusinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthti,nand-ecc-optrb-gpiosgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nsgpmc,device-widthbank-widthgpmc,mux-add-datagpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsenvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowervdds_dsi-supplyvdda_video-supplyremote-endpointdata-linesti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modeti,absolute-max-voltage-uvpolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-devicestartup-delay-usenable-active-highvin-supplyreset-gpioslabellinux,codewakeup-sourceti,modelti,mcbsplinux,default-triggerbacklightenable-gpiospwmsbrightness-levelsdefault-brightness-level