,R8((n(9sipeed,lichee-pi-4asipeed,lichee-module-4athead,th1520 &Sipeed Lichee Pi 4Acpus ,-cpu@0thead,c910riscv?cpu Krv64imafdcUrv64i(dimafdczicntrzicsrzifenceizihpmy}@@ riscv,sv39interrupt-controllerriscv,cpu-intccpu@1thead,c910riscv?cpu Krv64imafdcUrv64i(dimafdczicntrzicsrzifenceizihpmy}@@ riscv,sv39interrupt-controllerriscv,cpu-intccpu@2thead,c910riscv?cpu Krv64imafdcUrv64i(dimafdczicntrzicsrzifenceizihpmy}@@ riscv,sv39interrupt-controllerriscv,cpu-intccpu@3thead,c910riscv?cpu Krv64imafdcUrv64i(dimafdczicntrzicsrzifenceizihpmy}@@ riscv,sv39interrupt-controllerriscv,cpu-intcl2-cachecache@+pmu riscv,pmu9  U   Hn      !"#$%&'()*oscillator fixed-clockosc_24mn632k-oscillator fixed-clockosc_32ksoc simple-bus interrupt-controller@ffd8000000"thead,th1520-plicthead,c900-plicy@         timer@ffdc000000$thead,th1520-clintthead,c900-clinty@spi@ffe700c000!thead,th1520-spisnps,dw-apb-ssiy66 okayserial@ffe7014000snps,dw-apb-uarty@$U7baudclkapb_pclk*4okaymmc@ffe7080000thead,th1520-dwcmshcy>+coreokayAK =Yhv~mmc@ffe7090000thead,th1520-dwcmshcy @+coreokayAK =mmc@ffe70a0000thead,th1520-dwcmshcy G+core disabledserial@ffe7f00000snps,dw-apb-uarty%U8baudclkapb_pclk*4 disabledserial@ffe7f04000snps,dw-apb-uarty@'U:baudclkapb_pclk*4 disabledgpio@ffe7f34000snps,dw-apb-gpioy@ ?gpio-controller@0snps,dw-apb-gpio-port y:gpio@ffe7f38000snps,dw-apb-gpioy 1gpio-controller@0snps,dw-apb-gpio-port y;gpio@ffec005000snps,dw-apb-gpioyP =gpio-controller@0snps,dw-apb-gpio-port y8gpio@ffec006000snps,dw-apb-gpioy` >gpio-controller@0snps,dw-apb-gpio-port y9serial@ffec010000snps,dw-apb-uarty@&U9baudclkapb_pclk*4 disabledclock-controller@ffef010000thead,th1520-clk-apydma-controller@ffefc00000snps,axi-dma-1.01aycore-clkcfgr-clkokaytimer@ffefc32000snps,dw-apb-timery timer disabledtimer@ffefc32014snps,dw-apb-timery timer disabledtimer@ffefc32028snps,dw-apb-timery (timer disabledtimer@ffefc3203csnps,dw-apb-timery <timer disabledserial@fff7f08000snps,dw-apb-uarty@(U;baudclkapb_pclk*4 disabledserial@fff7f0c000snps,dw-apb-uarty@)U<baudclkapb_pclk*4 disabledtimer@ffffc33000snps,dw-apb-timery0timer disabledtimer@ffffc33014snps,dw-apb-timery0timer disabledtimer@ffffc33028snps,dw-apb-timery0(timer disabledtimer@ffffc3303csnps,dw-apb-timery0<timer disabledgpio@fffff41000snps,dw-apb-gpioy gpio-controller@0snps,dw-apb-gpio-port yLgpio@fffff52000snps,dw-apb-gpioy  gpio-controller@0snps,dw-apb-gpio-port y7memory@0?memoryyaliases/soc/gpio@ffec005000/soc/gpio@ffec006000!/soc/gpio@ffe7f34000'/soc/gpio@ffe7f38000-/soc/serial@ffe70140005/soc/serial@ffe7f00000=/soc/serial@ffec010000E/soc/serial@ffe7f04000M/soc/serial@fff7f08000U/soc/serial@fff7f0c000]/soc/spi@ffe700c000chosenbserial0:115200n8 compatible#address-cells#size-cellsmodeltimebase-frequencydevice_typeriscv,isariscv,isa-baseriscv,isa-extensionsregi-cache-block-sizei-cache-sizei-cache-setsd-cache-block-sized-cache-sized-cache-setsnext-level-cachemmu-typeinterrupt-controller#interrupt-cellsphandlecache-levelcache-unifiedriscv,event-to-mhpmcountersriscv,event-to-mhpmeventriscv,raw-event-to-mhpmcountersclock-output-names#clock-cellsclock-frequencyinterrupt-parentdma-noncoherentrangesinterrupts-extendedriscv,ndevinterruptsclocksstatusclock-namesreg-shiftreg-io-widthbus-widthmax-frequencymmc-hs400-1_8vnon-removableno-sdiono-sdgpio-controller#gpio-cellsngpios#dma-cellsdma-channelssnps,block-sizesnps,prioritysnps,dma-masterssnps,data-widthsnps,axi-max-burst-lengpio0gpio1gpio2gpio3serial0serial1serial2serial3serial4serial5spi0stdout-path