`8[(.[,Cubietech Cubieboard4.2cubietech,a80-cubieboard4allwinner,sun9i-a80aliases=/soc@20000/ethernet@830000G/soc@20000/serial@7000000cpuscpu@02arm,cortex-a7Ocpu[l|allwinner,sun9i-a80-smpcpu@12arm,cortex-a7Ocpu[l|allwinner,sun9i-a80-smpcpu@22arm,cortex-a7Ocpu[l|allwinner,sun9i-a80-smpcpu@32arm,cortex-a7Ocpu[l|allwinner,sun9i-a80-smpcpu@1002arm,cortex-a15Ocpu[l|allwinner,sun9i-a80-smpcpu@1012arm,cortex-a15Ocpu[l|allwinner,sun9i-a80-smpcpu@1022arm,cortex-a15Ocpu[l|allwinner,sun9i-a80-smpcpu@1032arm,cortex-a15Ocpu[l|allwinner,sun9i-a80-smptimer2arm,armv7-timer0   ln6clocks clk-24M 2fixed-clockln6osc24Mclk-32k2fixed-factor-clockosc32kmii-phy-tx-clk 2fixed-clockl}x@ mii_phy_txgmac-int-tx-clk 2fixed-clocklsY@ gmac_int_txclk@8000302allwinner,sun7i-a20-gmac-clk0gmac_txclk@80014102allwinner,sun9i-a80-cpus-clk  cpus clk-ahbs2fixed-factor-clock ahbs clk@800141c2allwinner,sun8i-a23-apb0-clk apbs clk@8001428#2allwinner,sun9i-a80-apbs-gates-clk( 8 apbs_pioapbs_irapbs_timerapbs_rsbapbs_uartapbs_1wireapbs_i2c0apbs_i2c1apbs_ps2_0apbs_ps2_1apbs_dmaapbs_i2s0apbs_i2s1apbs_twd?clk@8001450P2allwinner,sun4i-a10-mod0-clkr_1wireclk@8001454T2allwinner,sun4i-a10-mod0-clkr_ir@display-engine#2allwinner,sun9i-a80-display-engine *okaysoc@20000 2simple-bus sram@20000 2mmio-sram smp-sram@10002allwinner,sun9i-a80-smp-sramethernet@8300002allwinner,sun7i-a20-gmacT R1macirq  aAstmmacethallwinner_gmac_txM  Tstmmaceth`iz*okaydefault rgmii-idmdio2snps,dwmac-mdioethernet-phy@1usb@a00000&2allwinner,sun9i-a80-ehcigeneric-ehci HMusb *disabledusb@a00400&2allwinner,sun9i-a80-ohcigeneric-ohci IMusb *disabledphy@a008002allwinner,sun9i-a80-usb-phyAphyMTphy *disabledusb@a01000&2allwinner,sun9i-a80-ehcigeneric-ehci JMusb *disabledphy@a018002allwinner,sun9i-a80-usb-phy Aphyhsic_12Mhsic_480MM Tphyhsic *disabledhsicusb@a02000&2allwinner,sun9i-a80-ehcigeneric-ehci  LMusb *disabledusb@a02400&2allwinner,sun9i-a80-ohcigeneric-ohci$ MMusb *disabledphy@a028002allwinner,sun9i-a80-usb-phy(  Aphyhsic_12Mhsic_480MM Tphyhsic *disabledclock@a080002allwinner,sun9i-a80-usb-clks  ` Abushosccpucfg@17000002allwinner,sun9i-a80-cpucfgpcrypto@1c020002allwinner,sun9i-a80-crypto  PM  S .Abusmodmmc@1c0f0002allwinner,sun9i-a80-mmc  ! # "AahbmmcoutputsampleMTahb <*okaydefaultmmc@1c100002allwinner,sun9i-a80-mmc  $ & %AahbmmcoutputsampleMTahb =*okaydefault$/mmc@1c110002allwinner,sun9i-a80-mmc  ' ) (AahbmmcoutputsampleMTahb >*okaydefault/=mmc@1c120002allwinner,sun9i-a80-mmc   * , +AahbmmcoutputsampleMTahb ? *disabledclk@1c13000#2allwinner,sun9i-a80-mmc-config-clk0 TM 0mmc0_configmmc1_configmmc2_configmmc3_configinterrupt-controller@1c41000 2arm,gic-400  @ ` Nc  cci@1c90000 2arm,cci-400 slave-if@40002arm,cci-400-ctrl-iftace@slave-if@50002arm,cci-400-ctrl-iftacePpmu@90002arm,cci-400-pmu,r1P<clock@30000002allwinner,sun9i-a80-de-clks0 7 6 k AmoddrambusM  display-frontend@3100000%2allwinner,sun9i-a80-display-frontend ]   AahbmodramM  portsport@1endpoint!)display-frontend@3140000%2allwinner,sun9i-a80-display-frontend ^    AahbmodramM portsport@1endpoint",display-backend@3200000$2allwinner,sun9i-a80-display-backend  _    AahbmodramM portsport@0endpoint@0#*endpoint@1$-port@1endpoint%/display-backend@3240000$2allwinner,sun9i-a80-display-backend$ `    AahbmodramM portsport@0endpoint@0&+endpoint@1'.port@1endpoint(1deu@33000002allwinner,sun9i-a80-deu0 \    AahbmodramM portsport@0endpoint)!port@1endpoint@0*#endpoint@1+&deu@33400002allwinner,sun9i-a80-deu4 \    AahbmodramM portsport@0endpoint,"port@1endpoint@0-$endpoint@1.'drc@34000002allwinner,sun9i-a80-drc@ [    AahbmodramM portsport@0endpoint/%port@1endpoint04drc@34400002allwinner,sun9i-a80-drcD [   AahbmodramM portsport@0endpoint1(port@1endpoint26lcd-controller@3c000002allwinner,sun9i-a80-tcon-lcd V f : Aahbtcon-ch0M    Tlcdedplvdstcon0-pixel-clockdefault3portsport@0endpoint40port@1endpoint5Klcd-controller@3c100002allwinner,sun9i-a80-tcon-tv W g ; Aahbtcon-ch1M  Tlcdedpportsport@0endpoint62port@1clock@60000002allwinner,sun9i-a80-ccu Ahosclosc timer@6000c002allwinner,sun4i-a10-timer Hwatchdog@6000ca02allwinner,sun6i-a31-wdt  pinctrl@60008002allwinner,sun9i-a80-pinctrl< x oAapbhoscloscNc789:;gmac-rgmii-pinsBPA0PA1PA2PA3PA4PA5PA7PA8PA9PA10PA12PA13PA15PA16PA17$gmac-(i2c3-pins PG10PG11$i2c3=lcd0-rgb888-pinsPD0PD1PD2PD3PD4PD5PD6PD7PD8PD9PD10PD11PD12PD13PD14PD15PD16PD17PD18PD19PD20PD21PD22PD23PD24PD25PD26PD27$lcd03mmc0-pinsPF0PF1PF2PF3PF4PF5$mmc0-<mmc1-pinsPG0PG1PG2PG3PG4PG5$mmc1-<mmc2-8bit-pins3PC6PC7PC8PC9PC10PC11PC12PC13PC14PC15PC16$mmc2-(<uart0-ph-pins PH12PH13$uart0<uart4-pinsPG12PG13PG14PG15$uart4serial@70000002snps,dw-apb-uart IS |M -*okaydefault<serial@70004002snps,dw-apb-uart IS }M . *disabledserial@70008002snps,dw-apb-uart IS ~M / *disabledserial@7000c002snps,dw-apb-uart  IS M 0 *disabledserial@70010002snps,dw-apb-uart IS M 1 *disabledserial@70014002snps,dw-apb-uart IS M 2 *disabledi2c@70028002allwinner,sun6i-a31-i2c(  wM ( *disabledi2c@7002c002allwinner,sun6i-a31-i2c,  xM ) *disabledi2c@70030002allwinner,sun6i-a31-i2c0  yM * *disabledi2c@70034002allwinner,sun6i-a31-i2c4  zM +*okaydefault=Ii2c@70038002allwinner,sun6i-a31-i2c8  {M , *disabledwatchdog@80010002allwinner,sun6i-a31-wdt  $prcm@80014002allwinner,sun9i-a80-prcmreset@80014b0 2allwinner,sun6i-a31-clock-resetAinterrupt-controller@80015a02allwinner,sun9i-a80-nmiNc  Eir@80020002allwinner,sun6i-a31-ir %default> ?@AapbirMA @*okayserial@80028002snps,dw-apb-uart( &IS?MA *disabledpinctrl@8002c002allwinner,sun9i-a80-r-pinctrl,-.?AapbhoscloscNc`BnCGr-ir-pinsPL6 $s_cir_rx>r-rsb-pinsPN0PN1$s_rsb-<Drsb@80034002allwinner,sun8i-a23-rsb4 '?l-MAdefaultD*okaypmic@3a3E2x-powers,axp809Ncregulatorsaldo1|-- vcc33-usbhaldo2w@w@vcc-pb-io-cam8aldo3dc1swvcc-pd9dc5ldo| 5vdd-cpus-09-usbhdcdc1|--vcc-3vdcdc2 5vdd-gpudcdc3| 5 vdd-cpuadcdc4| 5vdd-sys-usb0-hdmidcdc5|  vcc-dramdldo12Z2Z vcc-wifidldo2--vcc-plBeldo1OO vcc-dvdd-cameldo2w@w@vcc-pe:eldo3--vcc-pm-codec-io1Cldo_io0--vcc-pg;ldo_io1&%&%vcc-pa-gmac-2v57rtc_ldovcc-rtc-vdd1v8-ioswgpio*2x-powers,axp809-gpiox-powers,axp221-gpiopmic@7452x-powers,axp806EENcFregulatorsaldo1|--avccaldo2s_aldo2aldo3s_aldo3bldo1|vcc18-efuse-adc-display-csibldo2|vdd18-drampll-vcc18-pll-cpvddbldo3bldo4  vcc12-hsiccldo12Z2Z vcc-gmac-phycldo2** afvcc-camcldo3--vcc-io-wifi-codec-io2dcdca| 5 vdd-cpubdcdcd| 5vdd-vpudcdce|  vcc-bldo-codec-ldoinFsws_swcodec@e892x-powers,ac100codec2x-powers,ac100-codecG 4M_addaHrtc2x-powers,ac100-rtcEHcko1_rtccko2_rtccko3_rtcchosenserial0:115200n8leds 2gpio-ledsled-0cubieboard4:green:usrled-1cubieboard4:red:usrvga-connector2vga-connectorvga IportendpointJLvga-dac2corpro,gm7123adi,adv7123portsport@0endpointK5port@1endpointLJwifi-pwrseq2mmc-pwrseq-simple Aext_clock"G #address-cells#size-cellsinterrupt-parentmodelcompatibleethernet0serial0device_typecci-control-portclock-frequencyenable-methodreginterruptsarm,cpu-registers-not-fw-configuredranges#clock-cellsclock-output-namesphandleclock-divclock-multclocksclock-indicesallwinner,pipelinesstatusinterrupt-namesclock-namesresetsreset-namessnps,pblsnps,fixed-burstsnps,force_sf_dma_modepinctrl-namespinctrl-0phy-handlephy-modephy-supplyphysphy-names#phy-cellsphy_type#reset-cellsvmmc-supplybus-widthcd-gpiosvqmmc-supplymmc-pwrseqnon-removablecap-mmc-hw-resetinterrupt-controller#interrupt-cellsinterface-typeremote-endpointgpio-controller#gpio-cellsvcc-pa-supplyvcc-pb-supplyvcc-pc-supplyvcc-pd-supplyvcc-pe-supplyvcc-pf-supplyvcc-pg-supplyvcc-ph-supplypinsfunctiondrive-strengthbias-pull-upreg-shiftreg-io-widthvcc-pl-supplyvcc-pm-supplyregulator-always-onregulator-min-microvoltregulator-max-microvoltregulator-namebldoin-supplyregulator-enable-ramp-delaystdout-pathlabelddc-i2c-busvdd-supplyreset-gpios