/b8,`(,(9renesas,rzv2h-evkrenesas,r9a09g057h44renesas,r9a09g057 /&Renesas RZ/V2H EVK Board based on r9a09g057h44audio-clk fixed-clock,9XIcpus cpu@0arm,cortex-a55QUcpuarpscicpu@100arm,cortex-a55QUcpuarpscicpu@200arm,cortex-a55QUcpuarpscicpu@300arm,cortex-a55QUcpuarpscicache-controller-0cacheIpsciarm,psci-1.0arm,psci-0.2ysmcqextal-clk fixed-clock,9n6Irtxin-clk fixed-clock,9Isoc simple-bus pinctrl@10410000renesas,r9a09g057-pinctrlQA ` Ii2c0'I i2c1'I i2c2'I i2c3'I i2c6'$%I i2c7'&'Ii2c8'Iscif.SCIF_TXDSCIF_RXD3Isd1-pwr-en-hogLUS[ gsd1_pwr_ensd1Isd1_dat_cmd'.SD1DAT0SD1DAT1SD1DAT2SD1DAT3SD1CMDq3~sd1_clk.SD1CLK3~sd1_cd'Lclock-controller@10420000renesas,r9a09g057-cpgQB audio_extalrtxinqextal,Isystem-controller@10430000renesas,r9a09g057-sysQC  0 disabledtimer@11800000$renesas,r9a09g057-ostmrenesas,ostmQ  C mokaytimer@11801000$renesas,r9a09g057-ostmrenesas,ostmQ  D nokaytimer@14000000$renesas,r9a09g057-ostmrenesas,ostmQ  E ookaytimer@14001000$renesas,r9a09g057-ostmrenesas,ostmQ  F pokaytimer@12c00000$renesas,r9a09g057-ostmrenesas,ostmQ  G qokaytimer@12c01000$renesas,r9a09g057-ostmrenesas,ostmQ  H rokaytimer@12c02000$renesas,r9a09g057-ostmrenesas,ostmQ   I sokaytimer@12c03000$renesas,r9a09g057-ostmrenesas,ostmQ0  J tokaywatchdog@11c00400renesas,r9a09g057-wdtQKL pclkoscclk u disabledwatchdog@14400000renesas,r9a09g057-wdtQ@MN pclkoscclk vokaywatchdog@13000000renesas,r9a09g057-wdtQOP pclkoscclk w disabledwatchdog@13000400renesas,r9a09g057-wdtQQR pclkoscclk x disabledserial@11c01400renesas,scif-r9a09g057Ql2erirxitxibridriteitei-drirxi-edgetxi-edge fck okaydefaulti2c@14400400renesas,riic-r9a09g057Q@` teiritispistinakialitmoi   okay default9i2c@14400800renesas,riic-r9a09g057Q@` teiritispistinakialitmoi   okay default9i2c@14400c00renesas,riic-r9a09g057Q@ ` teiritispistinakialitmoi   okay default9i2c@14401000renesas,riic-r9a09g057Q@` teiritispistinakialitmoi   okay default9i2c@14401400renesas,riic-r9a09g057Q@` teiritispistinakialitmoi    disabledi2c@14401800renesas,riic-r9a09g057Q@` teiritispistinakialitmoi    disabledi2c@14401c00renesas,riic-r9a09g057Q@` teiritispistinakialitmoi   okay default9i2c@14402000renesas,riic-r9a09g057Q@ `  teiritispistinakialitmoi   okaydefault9i2c@11c01000renesas,riic-r9a09g057Q`   teiritispistinakialitmoi   okaydefault9interrupt-controller@14900000 arm,gic-v3 Q   Immc@15c00000renesas,sdhi-r9a09g057Q0coreclkhcdaclk  disabledmmc@15c10000renesas,sdhi-r9a09g057Q0coreclkhcdaclk okaydefaultstate_uhs)mmc@15c20000renesas,sdhi-r9a09g057Q0coreclkhcdaclk  disabledtimerarm,armv8-timerP7    %sec-physphysvirthyp-physhyp-virtaliasesK/soc/i2c@14400400P/soc/i2c@14400800U/soc/i2c@14400c00Z/soc/i2c@14401000_/soc/i2c@14401c00d/soc/i2c@14402000i/soc/i2c@11c01000n/soc/mmc@15c10000s/soc/serial@11c01400chosen{ignore_loglevelserial0:115200n8memory@48000000UmemoryQHmemory@240000000UmemoryQ@regulator1regulator-fixed fixed-3.3V2Z2ZIregulator-vccq-sdhi1regulator-gpio SDHI1 VccQ URw@2Z2Zw@I compatible#address-cells#size-cellsmodel#clock-cellsclock-frequencyphandleregdevice_typenext-level-cacheenable-methodcache-unifiedcache-sizecache-levelinterrupt-parentrangesclocksgpio-controller#gpio-cellsgpio-ranges#interrupt-cellsinterrupt-controllerpower-domainsresetspinmuxpinsrenesas,output-impedancegpio-hoggpiosoutput-highline-nameinput-enableslew-rateclock-names#reset-cells#power-domain-cellsstatusinterruptsinterrupt-namespinctrl-0pinctrl-namespinctrl-1vmmc-supplyvqmmc-supplybus-widthsd-uhs-sdr50sd-uhs-sdr104interrupts-extendedi2c0i2c1i2c2i2c3i2c6i2c7i2c8mmc1serial0bootargsstdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-boot-onregulator-always-ongpios-states