98(y4mediatek,mt8390-evkmediatek,mt8390mediatek,mt8188 +7MediaTek Genio-700 EVKcpus+cpu@0=cpuarm,cortex-a55IMpsci[w5k~@@cpu@100=cpuarm,cortex-a55IMpsci[w5k~@@ cpu@200=cpuarm,cortex-a55IMpsci[w5k~@@ cpu@300=cpuarm,cortex-a55IMpsci[w5k~@@ cpu@400=cpuarm,cortex-a55IMpsci[w5k~@@ cpu@500=cpuarm,cortex-a55IMpsci[w5k~@@ cpu@600=cpuarm,cortex-a78IMpsci[k~@@cpu@700=cpuarm,cortex-a78IMpsci[k~@@cpu-mapcluster0core0core1 core2 core3 core4 core5 core6core7idle-statespscicpu-off-larm,idle-state6G2X_hDcpu-off-barm,idle-state6G-Xhcluster-off-larm,idle-state6G7XhHcluster-off-barm,idle-state6G2Xhl2-cache0cachey@l2-cache1cachey@l3-cachecachey @oscillator-13m fixed-clock[]@clk13m1oscillator-26m fixed-clock[clk26m3oscillator-32k fixed-clock[clk32kopp-table-gpuoperating-points-v2Wopp-390000000>opp-431000000opp-4730000001h@ 'opp-515000000F Xopp-556000000!# hopp-598000000# <opp-640000000&% opp-670000000'c opp-700000000)' Lopp-730000000+ }opp-760000000-L `opp-790000000/q 4opp-8350000001 (ropp-8800000004s qopp-9150000006 Xopp-915000000-56 0opp-915000000-66 qpopp-9500000008ـ 5opp-950000000-58ـ X0opp-950000000-68ـ qppmu-a55arm,cortex-a55-pmu pmu-a78arm,cortex-a78-pmu psci arm,psci-1.0Tsmcthermal-zonescpu-little0-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalcooling-mapsmap0:H? cpu-little1-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalcooling-mapsmap0:H? cpu-little2-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalcooling-mapsmap0:H? cpu-little3-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalcooling-mapsmap0:H? cpu-big0-thermaldtripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalcooling-mapsmap0:?cpu-big1-thermaldtripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalcooling-mapsmap0:?apu-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalgpu-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalcooling-mapsmap0: ?gpu1-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalcooling-mapsmap0: ?adsp-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalvdo-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalinfra-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalcam1-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticalcam2-thermaltripstrip-alert0#L/Dpassivetrip-alert1#s/Dhottrip-crit#/ Dcriticaltimerarm,armv8-timer @   []@soc+ simple-busNinterrupt-controller@c000000 arm,gic-v3Uf } I    ppi-partitionsinterrupt-partition-0 interrupt-partition-1syscon@10000000 mediatek,mt8188-topckgensysconI syscon@10001000#mediatek,mt8188-infracfg-aosysconI!syscon@10003000mediatek,mt8188-pericfgsysconI0;pinctrl@10005000mediatek,mt8188-pinctrl`IP0iocfg0iocfg_rmiocfg_ltiocfg_lmiocfg_rteint}Uaudio-default-pinspins-cmd-datXefghijklmnrstuvyz|}~dptx-pinspins-cmd-dat.edp-panel-3v3-en-pinsZpins1eth-default-pinspins-ccpins-mdio pins-powerpins-rxdpins-txdeth-sleep-pinspins-ccpins-mdio$pins-rxdpins-txdi2c0-pinsGpins871i2c1-pinsPpins:91i2c2-pinsKpins<;1i2c3-pinsLpins>=1i2c4-pinsQpins@?1i2c5-pinsTpinsBA1i2c6-pinsUpinsDC1gpio-key-pinspins *+,mmc0-default-pins>pins-clkIfpins-cmd-dat$ epins-rstemmc0-uhs-pins?pins-clkIfpins-cmd-dat$ epins-dsIfpins-rstemmc1-default-pinsBpins-clkIfpins-cmd-dat epins-insertmmc1-uhs-pinsCpins-clkIfpins-cmd-dat emmc2-default-pinspins-clkIfpins-cmd-dat epins-pcm{mmc2-uhs-pinspins-clkIfpins-cmd-dat emmc2-eint-pinspins-dat1 emmc2-dat1-pinspins-dat1 epanel-default-pinspins-dcdc-Xpins-enoXpins-rstrt1715-int-pinsRpins_cmd0_dat  spi0-pinspins-spiEFGH$spi1-pinspins-spiKLMN$spi2-pins8pins-spiOPQR$touch-pinsJpins-irq $pins-resetuart0-pins4pins uart1-pins5pins!"uart2-pins6pins#$usb-default-pinspins-iddigS pins-validU pins-vbusTusb1-default-pinspins-validX pins-usb-hub-3v3-enpwifi-pwrseq-pinspins-wifi-enableXsyscon@10006000)mediatek,mt8188-scpsyssysconsimple-mfdI`power-controller!mediatek,mt8188-power-controller+cXpower-domain@0I+cpower-domain@1Iw ~mfgalt!+cpower-domain@2Icpower-domain@3Icpower-domain@4Icpower-domain@15Iw    3 4 = " " """"""""""""""""" ~topcamccuimgvencvdecwpecfgckcfgxoss-sram-cmnss-sram-v0l0ss-sram-v0l1ss-sram-ve0ss-sram-ve1ss-sram-ifass-sram-camss-sram-v1l5ss-sram-v1l6ss-sram-rdrss-iommuss-imgcamss-emiss-subcmn-rdrss-rsiss-cmn-l4ss-vdec1ss-wpess-cvdo-ve1!+cpower-domain@16IHw #######A~cfgckcfgxoss-galsss-cmnss-emiss-iommuss-larbss-rsiss-bus!+cpower-domain@20I0w $$$$8~cfgckcfgxoss-vpp1-g5ss-vpp1-g6ss-vpp1-l5ss-vpp1-l6!cpower-domain@23Iw%~ss-vdec!cpower-domain@22Iw&~ss-vdec!cpower-domain@29I w   ~camccubuscfgck!+cpower-domain@30I(w'''''6~ss-cam-l13ss-cam-l14ss-cam-mm0ss-cam-mm1ss-camsys!+cpower-domain@32I w'()$~ss-camb-subss-camb-rawss-camb-yuvcpower-domain@31Iw'*+$~ss-cama-subss-cama-rawss-cama-yuvcpower-domain@17I(w ,,,&~cfgckcfgxoss-larb2ss-larb3ss-gals!+cpower-domain@9I w @ ? ~bushdcp!cpower-domain@18I!cpower-domain@19I!cpower-domain@24I w----0~ss-ve1-larbss-ve1-coress-ve1-galsss-ve1-sram!cpower-domain@21Iw..~ss-wpe-l7ss-wpe-l7pce!cpower-domain@5I!w/ ~ss-pextp-fmemcpower-domain@7Iw 0 1~seninf0seninf1cpower-domain@6Icpower-domain@10I w E D ~busmain!+cpower-domain@11I !+cpower-domain@14Iw F~asm!cpower-domain@13I w S 0~a1sysintbusadspck!cpower-domain@12I !cpower-domain@8Iw/  ~ethermac!cwatchdog@10007000mediatek,mt8188-wdtIpsyscon@1000c000"mediatek,mt8188-apmixedsyssysconItimer@10017000,mediatek,mt8188-timermediatek,mt6765-timerIp w1pwrap@100240003mediatek,mt8188-pwrapmediatek,mt8195-pwrapsysconI@pwrapw!! ~spiwrappmicmediatek,mt6359}U adcmediatek,mt6359-auxadcmt6359codecregulatorsbuck_vs1vs1 5!-Ibuck_vgpu11vgpu117]- rIbuck_vmodemvmodem]*-buck_vpuvpu7]- rIbuck_vcorevcore ]- rIbuck_vs2vs2 5j-Ibuck_vpavpa /M`-,Dbuck_vproc2vproc27]L- rbuck_vproc1vproc17]L- rbuck_vcore_sshub vcore_sshub7buck_vgpu11_sshub vgpu11_sshub7ldo_vaud18vaud18w@w@-ldo_vsim1vsim1/M`-Eldo_vibrvibrO2Zldo_vrf12vrf12 Ildo_vusbvusb---I<ldo_vsram_proc2 vsram_proc2 ]L-Ildo_vio18vio18-IIldo_vcamiovcamioldo_vcn18vcn18w@w@-Ildo_vfe28vfe28**-xldo_vcn13vcn13  ldo_vcn33_1_bt vcn33_1_bt*5gldo_vcn33_1_wifi vcn33_1_wifi*5gldo_vaux18vaux18w@w@-Ildo_vsram_others vsram_others ]-ldo_vefusevefuseldo_vxo22vxo22w@!Ildo_vrfckvrfck`ldo_vrfck_1vrfckjldo_vbif28vbif28**-ldo_vio28vio28*2ZIldo_vemcvemc,@ 2Zldo_vemc_1vemc&%2Z@ldo_vcn33_2_bt vcn33_2_bt*5gIldo_vcn33_2_wifi vcn33_2_wifi*5gldo_va12va12O Ildo_va09va09 5Oldo_vrf18vrf18Pldo_vsram_md vsram_md ]*-ldo_vufsvufsIAldo_vm18vm18Ildo_vbbckvbbckOIldo_vsram_proc1 vsram_proc1 ]L-Ildo_vsim2vsim2/M`ldo_vsram_others_sshubvsram_others_sshub mt6359rtcmediatek,mt6358-rtcmailbox@10320000mediatek,mt8188-gceI2@w!Ymailbox@10330000mediatek,mt8188-gceI3@w!scp@10500000mediatek,mt8188-scp IPr sramcfg2okayclock-controller@10b91100mediatek,mt8188-adsp-audio26mI0serial@11001100*mediatek,mt8188-uartmediatek,mt6577-uartI w3! ~baudbusokay4defaultserial@11001200*mediatek,mt8188-uartmediatek,mt6577-uartI w3! ~baudbusokay5defaultserial@11001300*mediatek,mt8188-uartmediatek,mt6577-uartI w3! ~baudbusokay6defaultserial@11001400*mediatek,mt8188-uartmediatek,mt6577-uartI w3! ~baudbus disabledadc@11002000.mediatek,mt8188-auxadcmediatek,mt8173-auxadcI w!~main disabledsyscon@11003000"mediatek,mt8188-pericfg-aosysconI0/spi@1100a000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+Iw y !~parent-clksel-clkspi-clk disabledthermal-sensor@1100b000mediatek,mt8188-lvts-apI w!!7lvts-calib-data-1spi@11010000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+Iw y !2~parent-clksel-clkspi-clk disabledspi@11012000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+I w y !3~parent-clksel-clkspi-clkokay8defaultspi@11013000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+I0w y !4~parent-clksel-clkspi-clk disabledspi@11018000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+Iw y !8~parent-clksel-clkspi-clk disabledspi@11019000)mediatek,mt8188-spi-ipmmediatek,spi-ipm+Iw y !9~parent-clksel-clkspi-clk disabledusb@11200000'mediatek,mt8188-xhcimediatek,mtk-xhci I  > macippc9: ) *& v vw/ / ~sys_ckref_ckmcu_ck =;hTokayb<p=mmc@11230000(mediatek,mt8188-mmcmediatek,mt8183-mmc I# w !!!M!~sourcehclksource_cgcrypto_clkokaydefaultstate_uhs>|? H @A"mmc@11240000(mediatek,mt8188-mmcmediatek,mt8183-mmc I$w !!$~sourcehclksource_cg & okaydefaultstate_uhsB|C 0AN\ c DEthermal-sensor@11278000mediatek,mt8188-lvts-mcuI'w!!7lvts-calib-data-1i2c@11280000mediatek,mt8188-i2c I("lwF!7 ~maindma+okaydefaultG[touchscreen@5dgoodix,gt9271I]  v  HIdefaultJi2c@11281000mediatek,mt8188-i2c I("lwF!7 ~maindma+okaydefaultK[i2c@11282000mediatek,mt8188-i2c I( "lwF!7 ~maindma+okaydefaultL[clock-controller@11283000mediatek,mt8188-imp-iic-wrap-cI(0Fusb@112a0000'mediatek,mt8188-xhcimediatek,mtk-xhci I**> macippcM . -& v vw/ /~sys_ckref_ckmcu_ckokayb<usb@112b0000'mediatek,mt8188-xhcimediatek,mtk-xhci I++> macippcN , +& v vw/ /~sys_ckref_ckmcu_ck =;`Tokayb<spi@1132c000(mediatek,mt8188-normediatek,mt8186-norI2w X// ~spisfaxi X9 disabledi2c@11e00000mediatek,mt8188-i2c I"lwO!7 ~maindma+okaydefaultP[i2c@11e01000mediatek,mt8188-i2c I"lwO!7 ~maindma+okaydefaultQ|R[B@clock-controller@11e02000mediatek,mt8188-imp-iic-wrap-wI Ot-phy@11e30000.mediatek,mt8188-tphymediatek,generic-tphy-v3+Nokayusb-phy@0Iw  ~refda_refNt-phy@11e40000.mediatek,mt8188-tphymediatek,generic-tphy-v3+Nokayusb-phy@0Iw  ~refda_ref9usb-phy@700I w3 ~refda_ref:t-phy@11e80000.mediatek,mt8188-tphymediatek,generic-tphy-v3+Nokayusb-phy@0Iw  ~refda_refMi2c@11ec0000mediatek,mt8188-i2c I"lwS!7 ~maindma+okaydefaultT[i2c@11ec1000mediatek,mt8188-i2c I"lwS!7 ~maindma+okaydefaultU[clock-controller@11ec2000 mediatek,mt8188-imp-iic-wrap-enI Sefuse@11f20000%mediatek,mt8188-efusemediatek,efuseI+lvts1-calib@1acI@7gpu@13000000)mediatek,mt8188-maliarm,mali-valhall-jmI@wV0~} jobmmugpuWXXXcore0core1core2 disabledclock-controller@13fbf000mediatek,mt8188-mfgcfgIVclock-controller@14000000mediatek,mt8188-vppsys0I"clock-controller@14e00000mediatek,mt8188-wpesysI.clock-controller@14e02000mediatek,mt8188-wpesys-vpp0I clock-controller@14f00000mediatek,mt8188-vppsys1I$clock-controller@15000000mediatek,mt8188-imgsysIclock-controller@15110000 mediatek,mt8188-imgsys1-dip-topIclock-controller@15130000mediatek,mt8188-imgsys1-dip-nrIclock-controller@15220000mediatek,mt8188-imgsys-wpe1I"clock-controller@15330000mediatek,mt8188-ipesysI3clock-controller@15520000mediatek,mt8188-imgsys-wpe2IRclock-controller@15620000mediatek,mt8188-imgsys-wpe3Ibclock-controller@16000000mediatek,mt8188-camsysI'clock-controller@1604f000mediatek,mt8188-camsys-rawaI*clock-controller@1606f000mediatek,mt8188-camsys-yuvaI+clock-controller@1608f000mediatek,mt8188-camsys-rawbI(clock-controller@160af000mediatek,mt8188-camsys-yuvbI )clock-controller@17200000mediatek,mt8188-ccusysI clock-controller@1800f000mediatek,mt8188-vdecsys-socI&clock-controller@1802f000mediatek,mt8188-vdecsysI%clock-controller@1a000000mediatek,mt8188-vencsysI-syscon@1c01d000mediatek,mt8188-vdosys0sysconI  YY#syscon@1c100000mediatek,mt8188-vdosys1sysconI  YY,aliases*/soc/serial@11001100chosen2serial0:921600n8firmwareopteelinaro,optee-tzTsmcmemory@40000000=memoryI@reserved-memory+Noptee@43200000>IC memory@50000000shared-dma-poolIP>2memory@54600000>IT` memory@55000000shared-dma-poolIU@memory@57000000shared-dma-poolIW@regulator-0regulator-fixed5v_enLK@LK@ E JIregulator-1regulator-fixededp_panel_3v32Z2ZJ EdefaultZregulator-2regulator-fixed gpio_3v3_en2Z2Z E JIregulator-3regulator-fixedsdio_iow@w@JIregulator-4regulator-fixed sdio_card2Z2Z EJJIregulator-5regulator-fixed touch_3v32Z2Z EwJHregulator-6regulator-fixed usb_hub_3v32Z2Z Ep]'J[regulator-7regulator-fixedusb_hub_resetw@w@ En[=regulator-8regulator-fixed usb_p0_vbusLK@LK@ ETJregulator-9regulator-fixed usb_p1_vbusLK@LK@ EWJregulator-10regulator-fixed usb_p2_vbusLK@LK@J compatibleinterrupt-parent#address-cells#size-cellsmodeldevice_typeregenable-methodclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellsphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unified#clock-cellsclock-output-namesopp-sharedopp-hzopp-microvoltopp-supported-hwinterruptspolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-deviceranges#interrupt-cells#redistributor-regionsinterrupt-controlleraffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangespinmuxbias-pull-upoutput-highdrive-strengthinput-enableinput-disablebias-disabledrive-strength-microampbias-pull-downoutput-low#power-domain-cellsclocksclock-namesmediatek,infracfgmediatek,disable-extrst#io-channel-cellsmediatek,mic-type-0mediatek,mic-type-1regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modes#mbox-cellsmemory-regionstatuspinctrl-0pinctrl-namesresetsnvmem-cellsnvmem-cell-names#thermal-sensor-cellsmediatek,pad-selectphysassigned-clocksassigned-clock-parentsmediatek,syscon-wakeupwakeup-sourcevusb33-supplyvbus-supplypinctrl-1bus-widthmax-frequencycap-mmc-highspeedmmc-hs200-1_8vmmc-hs400-1_8vsupports-cqecap-mmc-hw-resetno-sdiono-sdhs400-ds-delayvmmc-supplyvqmmc-supplynon-removablecap-sd-highspeedsd-uhs-sdr50sd-uhs-sdr104no-mmccd-gpiosclock-divinterrupts-extendedirq-gpiosreset-gpiosAVDD28-supplyVDDIO-supply#phy-cellsinterrupt-namesoperating-points-v2power-domainspower-domain-namesmboxesmediatek,gce-client-regserial0stdout-pathno-mapgpioenable-active-highstartup-delay-usvin-supply