v8g(g`google,dojo-sku7google,dojo-sku5google,dojo-sku3google,dojo-sku1google,dojomediatek,mt8195 +7HP Dojo (sku 1, 3, 5, 7) board =convertiblealiasesJ/soc/dp-intf@1c015000S/soc/dp-intf@1c113000\/soc/mailbox@10320000a/soc/mailbox@10330000f/soc/hdr-engine@1c114000m/soc/mutex@1c016000t/soc/mutex@1c101000{/soc/vpp-merge@1c10c000/soc/vpp-merge@1c10d000/soc/vpp-merge@1c10e000/soc/vpp-merge@1c10f000/soc/vpp-merge@1c110000/soc/dma-controller@1c104000/soc/dma-controller@1c105000/soc/dma-controller@1c106000/soc/dma-controller@1c107000/soc/dma-controller@1c108000/soc/dma-controller@1c109000/soc/dma-controller@1c10a000/soc/dma-controller@1c10b000/soc/i2c@11e00000/soc/i2c@11e01000/soc/i2c@11e02000/soc/i2c@11e03000 /soc/i2c@11e04000/soc/i2c@11d00000/soc/i2c@11d02000/soc/mmc@11230000/soc/mmc@11240000#/soc/serial@11001100cpus+cpu@0+cpuarm,cortex-a557;psciI]ec3@m4@@ cpu@100+cpuarm,cortex-a557;psciI]ec3@m4@@ cpu@200+cpuarm,cortex-a557;psciI]ec3@m4@@ cpu@300+cpuarm,cortex-a557;psciI]ec3@m4@@cpu@400+cpuarm,cortex-a787;psciI]fm@@  cpu@500+cpuarm,cortex-a787;psciI]fm@@  cpu@600+cpuarm,cortex-a787;psciI]fm@@  cpu@700+cpuarm,cortex-a787;psciI]fm@@  cpu-mapcluster0core0 core1 core2 core3core4core5core6core7idle-statespscicpu-retention-larm,idle-state,CT2e_uDcpu-retention-barm,idle-state,CT-eucpu-off-larm,idle-state,CT7euHcpu-off-barm,idle-state,CT2eul2-cache0cache@l2-cache1cache@ l3-cachecache @dsu-pmu arm,dsu-pmu  faildmic-codec dmic-codec2mt8195-soundokay}DL10_FEDPTX_BEETDM1_IN_BEETDM2_IN_BEETDM1_OUT_BEETDM2_OUT_BEUL_SRC1_BEAFE_SOF_DL2AFE_SOF_DL3AFE_SOF_UL4AFE_SOF_UL5default[HeadphoneHPOLHeadphoneHPORIN1PHeadset MicRight SpkRight BE_OUTLeft SpkLeft BE_OUT'mediatek,mt8195_mt6359_max98390_rt56827m8195_m98390_5682smm-dai-link ,ETDM1_IN_BE6cpuhs-playback-dai-link ,ETDM1_OUT_BE6cpucodecLhs-capture-dai-link ,ETDM2_IN_BE6cpucodecLspk-playback-dai-link ,ETDM2_OUT_BE6cpucodecLdisplayport-dai-link,DPTX_BEcodecLfixed-factor-clock-13mfixed-factor-clockVcjtclk13m3oscillator-26m fixed-clockV]clk26moscillator-32k fixed-clockV]clk32kperformance-controller@11bc10mediatek,cpufreq-hw 7 0 opp-table-gpuoperating-points-v2~opp-390000000> hopp-410000000p opp-431000000 opp-4730000001h@ <opp-515000000F <opp-556000000!# Ҧopp-598000000# opp-640000000&% opp-670000000'c opp-700000000)' Lopp-730000000+ }opp-760000000-L `opp-790000000/q 4opp-82000000005 opp-8500000002 @opp-8800000004s qpmu-a55arm,cortex-a55-pmu pmu-a78arm,cortex-a78-pmu psci arm,psci-1.0Bsmctimerarm,armv8-timer @   soc+ simple-businterrupt-controller@c000000 arm,gic-v3  7    ppi-partitionsinterrupt-partition-0; interrupt-partition-1;syscon@10000000 mediatek,mt8195-topckgensyscon7V"syscon@10001000#mediatek,mt8195-infracfg_aosyscon7VD#syscon@10003000mediatek,mt8195-pericfgsyscon70VIpinctrl@10005000mediatek,mt8195-pinctrl7PBQiocfg0iocfg_bmiocfg_bliocfg_briocfg_lmiocfg_rbiocfg_tleint[kwdefault>I2S_SPKR_MCLKI2S_SPKR_DATAINI2S_SPKR_LRCKI2S_SPKR_BCLKEC_AP_INT_ODLAP_FLASH_WP_LTCHPAD_INT_ODLEDP_HPD_1V8AP_I2C_CAM_SDAAP_I2C_CAM_SCLAP_I2C_TCHPAD_SDA_1V8AP_I2C_TCHPAD_SCL_1V8AP_I2C_AUD_SDAAP_I2C_AUD_SCLAP_I2C_TPM_SDA_1V8AP_I2C_TPM_SCL_1V8AP_I2C_TCHSCR_SDA_1V8AP_I2C_TCHSCR_SCL_1V8EC_AP_HPD_ODPCIE_NVME_RST_LPCIE_NVME_CLKREQ_ODLPCIE_RST_1V8_LPCIE_CLKREQ_1V8_ODLPCIE_WAKE_1V8_ODLCLK_24M_CAM0CAM1_SEN_ENAP_I2C_PWR_SCL_1V8AP_I2C_PWR_SDA_1V8AP_I2C_MISC_SCLAP_I2C_MISC_SDAEN_PP5000_HDMI_XAP_HDMITX_HTPLGAP_HDMITX_SCL_1V8AP_HDMITX_SDA_1V8AP_RTC_CLK32KAP_EC_WATCHDOG_LSRCLKENA0SRCLKENA1PWRAP_SPI0_CS_LPWRAP_SPI0_CKPWRAP_SPI0_MOSIPWRAP_SPI0_MISOSPMI_SCLSPMI_SDAI2S_HP_DATAINI2S_HP_MCLKI2S_HP_BCKI2S_HP_LRCKI2S_HP_DATAOUTSD_CD_ODLEN_PP3300_DISP_XTCHSCR_RST_1V8_LTCHSCR_REPORT_DISABLEEN_PP3300_WLAN_XBT_KILL_1V8_LI2S_SPKR_DATAOUTWIFI_KILL_1V8_LBEEP_ONSCP_I2C_SENSOR_SCL_1V8SCP_I2C_SENSOR_SDA_1V8AUD_CLK_MOSIAUD_SYNC_MOSIAUD_DAT_MOSI0AUD_DAT_MOSI1AUD_DAT_MISO0AUD_DAT_MISO1AUD_DAT_MISO2SCP_VREQ_VAOAP_SPI_GSC_TPM_CLKAP_SPI_GSC_TPM_MOSIAP_SPI_GSC_TPM_CS_LAP_SPI_GSC_TPM_MISOEN_PP1000_CAM_XAP_EDP_BKLTENUSB3_HUB_RST_LWLAN_ALERT_ODLEC_IN_RW_ODLGSC_AP_INT_ODLHP_INT_ODLCAM0_RST_LCAM1_RST_LTCHSCR_INT_1V8_LCAM1_DET_LRST_ALC1011_LBL_PWM_1V8UART_AP_TX_DBG_RXUART_DBG_TX_AP_RXEN_SPKRAP_EC_WARM_RST_REQUART_SCP_TX_DBGCON_RXUART_DBGCON_TX_SCP_RXKPCOL0MT6315_GPU_INTMT6315_PROC_BC_INTSD_CMDSD_CLKSD_DAT0SD_DAT1SD_DAT2SD_DAT3EMMC_DAT7EMMC_DAT6EMMC_DAT5EMMC_DAT4EMMC_RSTBEMMC_CMDEMMC_CLKEMMC_DAT3EMMC_DAT2EMMC_DAT1EMMC_DAT0EMMC_DSLMT6360_INT_ODLSCP_JTAG0_TRSTNAP_SPI_EC_CS_LAP_SPI_EC_CLKAP_SPI_EC_MOSIAP_SPI_EC_MISOSCP_JTAG0_TMSSCP_JTAG0_TCKSCP_JTAG0_TDOSCP_JTAG0_TDIAP_SPI_FLASH_CS_LAP_SPI_FLASH_CLKAP_SPI_FLASH_MOSIAP_SPI_FLASH_MISOaudio-default-pinspins-cmd-datDEFGHIJK<12345pins-hp-jack-int-odlYecr50-irq-default-pinsmpins-gsc-ap-int-odlXcros-ec-irq-default-pins?pins-ec-ap-int-odleedptx-default-pinspins-cmd-datdisp-pwm0-default-pinsCpins-disp-pwmRadptx-default-pinspins-cmd-dati2c0-default-pinsdpins-bus i2c1-default-pinsepins-bus  i2c2-default-pinshpins-bus  i2c3-default-pinslpins-busi2c4-default-pinsnpins-busi2c5-default-pins`pins-busi2c7-default-pinsapins-busmmc0-default-pinsLpins-cmd-dat$~}|{wvutyepins-clkz fpins-rstxemmc0-uhs-pinsMpins-cmd-dat$~}|{wvutyepins-clkz fpins-ds fpins-rstxemmc1-detect-pinsQpins-insert6mmc1-default-pinsPpins-cmd-datnpqrsepins-clko fnor-default-pins^pins-ck-io  pins-cspcie0-default-pinsZpins-bus pcie1-default-pins]pins-bus panel-pwr-default-pinspins-vreg-en7pio-default-pinspins-wifi-enable:pins-low-power-pd,./0ABCD pins-low-power-pupd<MNOPSUZ[]^_`hik epins-low-power-hdmi-disable  ! pins-low-power-hdmi-rsel-disable"# $rt1019p-default-pinspins-amp-sdbd'scp-default-pins5pins-vreqLspi0-default-pins>pins-cs-mosi-clk pins-miso subpmic-default-pinsbpins-subpmic-int-ntrackpad-default-pinsfpins-int-ntouchscreen-default-pinsopins-int-n\epins-rst8pins-report-sw9'syscon@10006000)mediatek,mt8195-scpsyssysconsimple-mfd7`power-controller!mediatek,mt8195-power-controller+27power-domain@87+2F power-domain@97 c!"Tmfgalt`#+2F$power-domain@107 2power-domain@117 2power-domain@127 2power-domain@137 2power-domain@1472power-domain@157c"""" "@"A"K"% % %%%%%%%%%%%%%%%%% Tvppsysvppsys1vppsys2vppsys3vppsys4vppsys5vppsys6vppsys7vppsys0-0vppsys0-1vppsys0-2vppsys0-3vppsys0-4vppsys0-5vppsys0-6vppsys0-7vppsys0-8vppsys0-9vppsys0-10vppsys0-11vppsys0-12vppsys0-13vppsys0-14vppsys0-15vppsys0-16vppsys0-17vppsys0-18`#+2power-domain@247c&Tvdec1-0`#2power-domain@277c' Tvenc1-larb`#2power-domain@1678c"($(%(&('((()DTvdosys0vdosys0-0vdosys0-1vdosys0-2vdosys0-3vdosys0-4vdosys0-5`#+2power-domain@177c"))Tvppsys1vppsys1-0vppsys1-1`#2power-domain@227 c****$Twepsys-0wepsys-1wepsys-2wepsys-3`#2power-domain@237c+Tvdec0-0`#2power-domain@257c,Tvdec2-0`#2power-domain@267c- Tvenc0-larb`#2power-domain@187 c"...&Tvdosys1vdosys1-0vdosys1-1vdosys1-2`#+2power-domain@197`#2power-domain@207`#2power-domain@217c"QThdmi_tx2power-domain@287c//  Timg-0img-1`#+2power-domain@2972power-domain@307c"/0Tipeipe-0ipe-1`#2power-domain@317(c11111Tcam-0cam-1cam-2cam-3cam-4`#+2power-domain@327 2power-domain@337!2power-domain@347"2power-domain@07`#2power-domain@17`#2power-domain@272power-domain@372power-domain@47c"5"7Tcsi_rx_topcsi_rx_top12power-domain@57c2 Tether2power-domain@67c"X"n Tadspadsp1+`#2power-domain@77 c"g"""n#2Taudioaudio1audio2audio3`#2watchdog@10007000mediatek,mt8195-wdtr7pD<syscon@1000c000"mediatek,mt8195-apmixedsyssyscon7V!timer@10017000,mediatek,mt8195-timermediatek,mt6765-timer7p c3pwrap@10024000mediatek,mt8195-pwrapsyscon7@Qpwrapc## Tspiwrap"$"pmicmediatek,mt6359 adcmediatek,mt6359-auxadcmt6359codecregulatorsbuck_vs1vs1 5%!=Ybuck_vgpu11vgpu11 %7m= Ybuck_vmodemvmodem %m*=buck_vpuvpu %7m= Ybuck_vcorevcore % m= Ybuck_vs2vs2 5%j=Ybuck_vpavpa  %7=,buck_vproc2vproc2 %7mL= buck_vproc1vproc1 %7mL= buck_vcore_sshub vcore_sshub %7buck_vgpu11_sshub vgpu11_sshub dp%dpYldo_vaud18vaud18 w@%w@=ldo_vsim1vsim1 %/M`ldo_vibrvibr O%2Zldo_vrf12vrf12 % Yldo_vusbvusb -%-=YJldo_vsram_proc2 vsram_proc2  %mL=Yldo_vio18vio18 %=Yildo_vcamiovcamio %ldo_vcn18vcn18 w@%w@=ldo_vfe28vfe28 *%*=xldo_vcn13vcn13 % ldo_vcn33_1_bt vcn33_1_bt *%5gldo_vcn33_1_wifi vcn33_1_wifi *%5gldo_vaux18vaux18 w@%w@=Yldo_vsram_others vsram_others q% qm=$ldo_vefusevefuse %ldo_vxo22vxo22 w@%!Yldo_vrfckvrfck `%ldo_vrfck_1vrfck %jldo_vbif28vbif28 *%*=ldo_vio28vio28 *%2ZYldo_vemcvemc ,@ %2Zldo_vemc_1vemc &%%2ZNldo_vcn33_2_bt vcn33_2_bt *%5gldo_vcn33_2_wifi vcn33_2_wifi *%5gldo_va12va12 O% Yldo_va09va09 5%Oldo_vrf18vrf18 %Pldo_vsram_md vsram_md  %m*=ldo_vufsvufs %YOldo_vm18vm18 %Yldo_vbbckvbbck %Oldo_vsram_proc1 vsram_proc1  %mL=Yldo_vsim2vsim2 %/M`ldo_vsram_others_sshubvsram_others_sshub  %mt6359rtcmediatek,mt6358-rtcspmi@10027000mediatek,mt8195-spmi 7p Qpmifspmimstc##"E(Tpmif_sys_ckpmif_tmr_ckspmimst_clk_mux"$"+mt6315@6mediatek,mt6315-regulator7regulatorsvbuck1vbuck1Vbcpu %7=mj Y mt6315@7mediatek,mt6315-regulator7regulatorsvbuck1vbuck1Vgpu %7=mj  infra-iommu@10315000mediatek,mt8195-iommu-infra71PPPWmailbox@10320000mediatek,mt8195-gce72@c#mailbox@10330000mediatek,mt8195-gce73@c#scp@10500000mediatek,mt8195-scp07PrpQsramcfgl1tcmokaymediatek/mt8195/scp.img4default5cros-ec-rpmsggoogle,cros-ec-rpmsgcros-ec-rpmsgclock-controller@10720000mediatek,mt8195-scp_adsp7rV6dsp@10803000mediatek,mt8195-dsp 70 Qcfgsram,c"X"n"6"#KTadsp_selclk26m_ckaudio_local_busmainpll_d7_d2scp_adsp_audiodspaudio_h7rxtx89okay:;mailbox@10816000mediatek,mt8195-adsp-mbox7`8mailbox@10817000mediatek,mt8195-adsp-mbox7p9mt8195-afe-pcm@10890000mediatek,mt8195-audio7"76*< 1audiosysc!!""""""g"""#"n"e"a"b"c"d#26Tclk26mapll1_ckapll2_ckapll12_div0apll12_div1apll12_div2apll12_div3apll12_div9a1sys_hp_selaud_intbus_selaudio_h_selaudio_local_bus_seldptx_m_seli2so1_m_seli2so2_m_seli2si1_m_seli2si2_m_selinfra_ao_audio_26m_bscp_adsp_audiodspokay=]=serial@11001100*mediatek,mt8195-uartmediatek,mt6577-uart7 c# Tbaudbusokayserial@11001200*mediatek,mt8195-uartmediatek,mt6577-uart7 c# Tbaudbus disabledserial@11001300*mediatek,mt8195-uartmediatek,mt6577-uart7 c# Tbaudbus disabledserial@11001400*mediatek,mt8195-uartmediatek,mt6577-uart7 c# Tbaudbus disabledserial@11001500*mediatek,mt8195-uartmediatek,mt6577-uart7 c# Tbaudbus disabledserial@11001600*mediatek,mt8195-uartmediatek,mt6577-uart7 c# Tbaudbus disabledauxadc@11002000.mediatek,mt8195-auxadcmediatek,mt8173-auxadc7 c#Tmainokaysyscon@11003000"mediatek,mt8195-pericfg_aosyscon70V2spi@1100a000(mediatek,mt8195-spimediatek,mt6765-spi+7c""#Tparent-clksel-clkspi-clkokaydefault>~ec@0+google,cros-ec-spi7 default?-i2c-tunnelgoogle,cros-ec-i2c-tunnel+sbs-battery@bsbs,sbs-battery7 regulator@0google,cros-ec-regulator7mt_pmic_vmc_ldo O%6Sregulator@1google,cros-ec-regulator7mt_pmic_vmch_ldo )2%6Rtypecgoogle,cros-ec-typec+connector@0usb-c-connector7dualhostsourceconnector@1usb-c-connector7dualhostsourcekeyboard-controllergoogle,cros-ec-keyb! 4PN}0Y1 d"#(  \V |})   + ^a !%$' & + ,./-32*5 4 9    8 l j6  g itxc  qrs4[  thermal-sensor@1100b000mediatek,mt8195-lvts-ap7 c#*#p@A$|lvts-calib-data-1lvts-calib-data-2svs@1100bc00mediatek,mt8195-svs7c#TmainpB@(|svs-calibration-datat-calibration-data*#1svs_rstpwm@1100e0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwm77c"*#0TmainmmokaydefaultCpwm@1100f0002mediatek,mt8195-disp-pwmmediatek,mt8183-disp-pwm7c"+#NTmainmm disabledspi@11010000(mediatek,mt8195-spimediatek,mt6765-spi+7c""#3Tparent-clksel-clkspi-clk disabledspi@11012000(mediatek,mt8195-spimediatek,mt6765-spi+7 c""#4Tparent-clksel-clkspi-clk disabledspi@11013000(mediatek,mt8195-spimediatek,mt6765-spi+70c""#5Tparent-clksel-clkspi-clk disabledspi@11018000(mediatek,mt8195-spimediatek,mt6765-spi+7c""#<Tparent-clksel-clkspi-clk disabledspi@11019000(mediatek,mt8195-spimediatek,mt6765-spi+7c""#=Tparent-clksel-clkspi-clk disabledspi@1101d000mediatek,mt8195-spi-slave7c#RTspi"" disabledspi@1101e000mediatek,mt8195-spi-slave7c#STspi"" disabledethernet@11021000&mediatek,mt8195-gmacsnps,dwmac-5.10a7@macirq.Taxiapbmac_mainptp_refrmii_internalmac_cg0c22"R"S"T2 "R"S"T"""7#DEF    disabledmdiosnps,dwmac-mdio+stmmac-axi-config ( 8 HDrx-queues-config R hEqueue0 y queue1 y queue2 y queue3 y tx-queues-config  Fqueue0  y queue1  y queue2  y queue3  y usb@11201000#mediatek,mt8195-mtu3mediatek,mtu3 7 - > Qmacippc ?+c#/"#BTsys_ckref_ckmcu_ck GH Igokay host Jusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci7Qmac","-""$c#/"!#B$Tsys_ckref_ckmcu_ckdma_ckxhci_ckokay   &Kmmc@11230000(mediatek,mt8195-mmcmediatek,mt8183-mmc 7#c"##Tsourcehclksource_cgokay 2 < N _L  n }   defaultstate_uhsL M N Ommc@11240000(mediatek,mt8195-mmcmediatek,mt8183-mmc 7$c"##$Tsourcehclksource_cg""okay 2  6   defaultstate_uhsPQ P   R Smmc@11250000(mediatek,mt8195-mmcmediatek,mt8183-mmc 7%c" ##ITsourcehclksource_cg" " disabledthermal-sensor@11278000mediatek,mt8195-lvts-mcu7'c#*#p@A$|lvts-calib-data-1lvts-calib-data-2usb@11290000'mediatek,mt8195-xhcimediatek,mtk-xhci 7))> Qmacippc T"."/""$c2"!2$Tsys_ckref_ckmcu_ckdma_ckxhci_ck Ihokay   J &K usb@112a1000#mediatek,mt8195-mtu3mediatek,mtu3 7*-*> Qmacippc*?+"0"c2"2Tsys_ckref_ckmcu_ck U Iiokay host Jusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci7Qmac"1"c2Tsys_ckokay &Kusb@112b1000#mediatek,mt8195-mtu3mediatek,mtu3 7+-+> Qmacippc+?+"2"c2"2 Tsys_ckref_ckmcu_ck V Ijokay host Jusb@0'mediatek,mt8195-xhcimediatek,mtk-xhci7Qmac"3"c2 Tsys_ckokay  &Kpcie@112f0000*mediatek,mt8195-pciemediatek,mt8192-pcie+pci+7/@ Qpcie-mac -8́  7W A0c#V###&#+#K2/Tpl_250mtl_26mtl_96mtl_32kperi_26mperi_mem"G" X Ppcie-phy7*#1mac Z` mYYYYokaydefaultZinterrupt-controllerYpcie@112f8000*mediatek,mt8195-pciemediatek,mt8192-pcie+pci+7/@ Qpcie-mac -8́$$ $ $  7W A(c#W#X#Q2/Tpl_250mtl_26mtl_96mtl_32kperi_26mperi_mem"H" [ Ppcie-phy7*#1mac Z` m\\\\okaydefault]interrupt-controller\spi@1132c000(mediatek,mt8195-normediatek,mt8173-nor729c"o22 Tspisfaxi+okaydefault^flash@0jedec,spi-nor7u { efuse@11c10000%mediatek,mt8195-efusemediatek,efuse7+usb3-tx-imp@184,17 uusb3-rx-imp@184,27 tusb3-intr@1857 susb3-tx-imp@186,17 rusb3-rx-imp@186,27 qusb3-intr@1877 pusb2-intr-p0@188,17 usb2-intr-p1@188,27 usb2-intr-p2@189,17 usb2-intr-p3@189,27 pciephy-rx-ln1@190,17 |pciephy-tx-ln1-nmos@190,27 {pciephy-tx-ln1-pmos@191,17 zpciephy-rx-ln0@191,27 ypciephy-tx-ln0-nmos@192,17 xpciephy-tx-ln0-pmos@192,27 wpciephy-glb-intr@1937 vdp-data@1ac7lvts1-calib@1bc7@lvts2-calib@1d078Asvs-calib@5807dBsocinfo-data1@7a07t-phy@11c40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@07c"Tref Ut-phy@11c50000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@07c"Tref Vdsi-phy@11c800000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx7c mipi_tx0_pllV  disableddsi-phy@11c900000mediatek,mt8195-mipi-txmediatek,mt8183-mipi-tx7c mipi_tx1_pllV  disabledi2c@11d00000(mediatek,mt8195-i2cmediatek,mt8192-i2c 7"jc_#; Tmaindma+okay]default`i2c@11d01000(mediatek,mt8195-i2cmediatek,mt8192-i2c 7"jc_#; Tmaindma+ disabledi2c@11d02000(mediatek,mt8195-i2cmediatek,mt8192-i2c 7 "jc_#; Tmaindma+okay]defaultapmic@34mediatek,mt636074 IRQBdefaultbclock-controller@11d03000mediatek,mt8195-imp_iic_wrap_s70V_i2c@11e00000(mediatek,mt8195-i2cmediatek,mt8192-i2c 7"jcc#; Tmaindma+okay]defaultdi2c@11e01000(mediatek,mt8195-i2cmediatek,mt8192-i2c 7"jcc#; Tmaindma+okay] 0defaultetrackpad@15elan,ekth30007 defaultf gi2c@11e02000(mediatek,mt8195-i2cmediatek,mt8192-i2c 7 "jcc#; Tmaindma+okay]defaulthcodec@1a7 Y   i j krealtek,rt5682s amplifier@38maxim,max9839078 .d :Right amplifier@39maxim,max9839079 :Left i2c@11e03000(mediatek,mt8195-i2cmediatek,mt8192-i2c 70"jcc#; Tmaindma+okay]defaultltpm@50 google,cr507P Xdefaultmi2c@11e04000(mediatek,mt8195-i2cmediatek,mt8192-i2c 7@"jcc#; Tmaindma+okay]defaultntouchscreen@10 hid-over-i2c7 L \defaulto [  rg disabledtouchscreen@15 hid-over-i2c7 L \defaulto [  rgclock-controller@11e05000mediatek,mt8195-imp_iic_wrap_w7PVct-phy@11e30000.mediatek,mt8195-tphymediatek,generic-tphy-v3+7okayusb-phy@07 c" Trefda_ref Tusb-phy@7007c!" Trefda_ref ppqr|intrrx_imptx_imp [t-phy@11e40000.mediatek,mt8195-tphymediatek,generic-tphy-v3+okayusb-phy@07 c" Trefda_ref Gusb-phy@7007c!" Trefda_ref pstu|intrrx_imptx_imp Hphy@11e80000mediatek,mt8195-pcie-phy7Qsifpvwxyz{|G|glb_intrtx_ln0_pmostx_ln0_nmosrx_ln0tx_ln1_pmostx_ln1_nmosrx_ln17 okayXufs-phy@11fa0000.mediatek,mt8195-ufsphymediatek,mt8183-ufsphy7c Tunipromp  disabledgpu@13000000>mediatek,mt8195-malimediatek,mt8192-maliarm,mali-valhall-jm7@c}0 jobmmugpu }~(7 7 7 7 7 core0core1core2core3core4okay clock-controller@13fbf000mediatek,mt8195-mfgcfg7V}syscon@14000000mediatek,mt8195-vppsys0syscon7V %dma-controller@14001000mediatek,mt8195-mdp3-rdma7    7 c%<   display@14002000mediatek,mt8195-mdp3-fg7   c%display@14003000mediatek,mt8195-mdp3-stitch70 0c%display@14004000mediatek,mt8195-mdp3-hdr7@ @c%"display@14005000mediatek,mt8195-mdp3-aal7PF Pc% 7display@140060002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz7` ` %c% display@14007000mediatek,mt8195-mdp3-tdshp7p pc%#display@14008000mediatek,mt8195-mdp3-color7I c%$7display@14009000mediatek,mt8195-mdp3-ovl7J c%%7 display@1400a000mediatek,mt8195-mdp3-padding7 c%7display@1400b000mediatek,mt8195-mdp3-tcc7 c%dma-controller@1400c0004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot7   +c% 7 mutex@1400f000mediatek,mt8195-vpp-mutex7P c%7smi@14010000mediatek,mt8195-smi-sub-common7c%%%Tapbsmigals0 7smi@14011000mediatek,mt8195-smi-sub-common7c%%%Tapbsmigals0 7smi@14012000mediatek,mt8195-smi-common-vpp7  c%%%%Tapbsmigals0gals17larb@14013000mediatek,mt8195-smi-larb70  c%%Tapbsmi7iommu@14018000mediatek,mt8195-iommu-vpp78 Rc%Tbclk7clock-controller@14e00000mediatek,mt8195-wpesys7V*clock-controller@14e02000mediatek,mt8195-wpesys_vpp07 Vclock-controller@14e03000mediatek,mt8195-wpesys_vpp170Vlarb@14e04000mediatek,mt8195-smi-larb7@  c**Tapbsmi7larb@14e05000mediatek,mt8195-smi-larb7P  c**% Tapbsmigals7syscon@14f00000mediatek,mt8195-vppsys1syscon7V  )mutex@14f01000mediatek,mt8195-vpp-mutex7{  c)'7larb@14f02000mediatek,mt8195-smi-larb7   c))% Tapbsmigals7larb@14f03000mediatek,mt8195-smi-larb70  c))% Tapbsmigals7display@14f06000mediatek,mt8195-mdp3-split7`  `c))+),7display@14f07000mediatek,mt8195-mdp3-tcc7p  pc)dma-controller@14f08000mediatek,mt8195-mdp3-rdma7   c) 7 dma-controller@14f09000mediatek,mt8195-mdp3-rdma7   c)  7 dma-controller@14f0a000mediatek,mt8195-mdp3-rdma7   c)  7 display@14f0b000mediatek,mt8195-mdp3-fg7  c) display@14f0c000mediatek,mt8195-mdp3-fg7  c) display@14f0d000mediatek,mt8195-mdp3-fg7  c) display@14f0e000mediatek,mt8195-mdp3-hdr7  c)display@14f0f000mediatek,mt8195-mdp3-hdr7  c)display@14f10000mediatek,mt8195-mdp3-hdr7  c) display@14f11000mediatek,mt8195-mdp3-aal7i  c)7display@14f12000mediatek,mt8195-mdp3-aal7 j  c)7display@14f13000mediatek,mt8195-mdp3-aal70k  0c)!7display@14f140002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz7@  @ c)display@14f150002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz7P  P c)$display@14f160002mediatek,mt8195-mdp3-rszmediatek,mt8183-mdp3-rsz7`  ` c)%display@14f17000mediatek,mt8195-mdp3-tdshp7p  pc)display@14f18000mediatek,mt8195-mdp3-tdshp7  c)(display@14f19000mediatek,mt8195-mdp3-tdshp7  c))display@14f1a000mediatek,mt8195-mdp3-merge7  c)7display@14f1b000mediatek,mt8195-mdp3-merge7  c)7display@14f1c000mediatek,mt8195-mdp3-color7t  c)7display@14f1d000mediatek,mt8195-mdp3-color7  uc)7display@14f1e000mediatek,mt8195-mdp3-color7v  c)7display@14f1f000mediatek,mt8195-mdp3-ovl7w  c)7 display@14f20000mediatek,mt8195-mdp3-padding7  c)7display@14f21000mediatek,mt8195-mdp3-padding7  c)7display@14f22000mediatek,mt8195-mdp3-padding7   c)7dma-controller@14f230004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot70  0 c) 7 dma-controller@14f240004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot7@  @ c) 7 dma-controller@14f250004mediatek,mt8195-mdp3-wrotmediatek,mt8183-mdp3-wrot7P  P c) 7 clock-controller@15000000mediatek,mt8195-imgsys7V/larb@15001000mediatek,mt8195-smi-larb7   c///  Tapbsmigals7smi@15002000mediatek,mt8195-smi-sub-common7 c//%Tapbsmigals0 7smi@15003000mediatek,mt8195-smi-sub-common70c/// Tapbsmigals0 7clock-controller@15110000 mediatek,mt8195-imgsys1_dip_top7Vlarb@15120000mediatek,mt8195-smi-larb7   c/Tapbsmi7clock-controller@15130000mediatek,mt8195-imgsys1_dip_nr7Vclock-controller@15220000mediatek,mt8195-imgsys1_wpe7"Vlarb@15230000mediatek,mt8195-smi-larb7#   c/Tapbsmi7clock-controller@15330000mediatek,mt8195-ipesys73V0larb@15340000mediatek,mt8195-smi-larb74   c00Tapbsmi7clock-controller@16000000mediatek,mt8195-camsys7V1larb@16001000mediatek,mt8195-smi-larb7   c111 Tapbsmigals7larb@16002000mediatek,mt8195-smi-larb7   c11Tapbsmi7smi@16004000mediatek,mt8195-smi-sub-common7@c111Tapbsmigals0 7smi@16005000mediatek,mt8195-smi-sub-common7Pc11%Tapbsmigals0 7larb@16012000mediatek,mt8195-smi-larb7   cTapbsmi7 larb@16013000mediatek,mt8195-smi-larb70  cTapbsmi7 larb@16014000mediatek,mt8195-smi-larb7@  cTapbsmi7!larb@16015000mediatek,mt8195-smi-larb7P  cTapbsmi7!clock-controller@1604f000mediatek,mt8195-camsys_rawa7Vclock-controller@1606f000mediatek,mt8195-camsys_yuva7Vclock-controller@1608f000mediatek,mt8195-camsys_rawb7Vclock-controller@160af000mediatek,mt8195-camsys_yuvb7 Vclock-controller@16140000mediatek,mt8195-camsys_mraw7Vlarb@16141000mediatek,mt8195-smi-larb7  c11 Tapbsmigals7"larb@16142000mediatek,mt8195-smi-larb7   cTapbsmi7"clock-controller@17200000mediatek,mt8195-ccusys7 Vlarb@17201000mediatek,mt8195-smi-larb7   cTapbsmi7video-codec@18000000mediatek,mt8195-vcodec-dec  + 7@`video-codec@2000mediatek,mtk-vcodec-lat-soc7   c"A++"Tselvdeclattop"A"7video-codec@10000mediatek,mtk-vcodec-lat70  c"A++"Tselvdeclattop"A"7video-codec@25000mediatek,mtk-vcodec-core7PP  c"A&&"Tselvdeclattop"A"7larb@1800d000mediatek,mt8195-smi-larb7  c++Tapbsmi7larb@1800e000mediatek,mt8195-smi-larb7  c%+Tapbsmi7clock-controller@1800f000mediatek,mt8195-vdecsys_soc7V+larb@1802e000mediatek,mt8195-smi-larb7  c&&Tapbsmi7clock-controller@1802f000mediatek,mt8195-vdecsys7V&larb@1803e000mediatek,mt8195-smi-larb7  c%,Tapbsmi7clock-controller@1803f000mediatek,mt8195-vdecsys_core17V,clock-controller@190f3000mediatek,mt8195-apusys_pll70Vclock-controller@1a000000mediatek,mt8195-vencsys7V-larb@1a010000mediatek,mt8195-smi-larb7  c--Tapbsmi7video-codec@1a020000mediatek,mt8195-vcodec-enc7H `abcdvwxyU c- Tvenc_sel"@"7+jpgdec-mastermediatek,mt8195-jpgdec70 mnrstu+jpgdec@1a040000mediatek,mt8195-jpgdec-hw70 mnrstuWc-Tjpgdec7jpgdec@1a050000mediatek,mt8195-jpgdec-hw70 mnrstuXc-Tjpgdec7jpgdec@1b040000mediatek,mt8195-jpgdec-hw70 \c'Tjpgdec7clock-controller@1b000000mediatek,mt8195-vencsys_core17V'syscon@1c01a0005mediatek,mt8195-vdosys0mediatek,mt8195-mmsyssyscon7 V (jpgenc-mastermediatek,mt8195-jpgenc7 +jpgenc@1a030000mediatek,mt8195-jpgenc-hw7 ghilVc-Tjpgenc7jpgenc@1b030000mediatek,mt8195-jpgenc-hw7 [c'Tjpgenc7larb@1b010000mediatek,mt8195-smi-larb7  c''%  Tapbsmigals7ovl@1c0000002mediatek,mt8195-disp-ovlmediatek,mt8183-disp-ovl7|7c(  rdma@1c002000mediatek,mt8195-disp-rdma7 ~7c(   color@1c0030006mediatek,mt8195-disp-colormediatek,mt8173-disp-color707c( 0ccorr@1c0040006mediatek,mt8195-disp-ccorrmediatek,mt8192-disp-ccorr7@7c( @aal@1c0050002mediatek,mt8195-disp-aalmediatek,mt8183-disp-aal7P7c( Pgamma@1c0060006mediatek,mt8195-disp-gammamediatek,mt8183-disp-gamma7`7c( `dither@1c0070008mediatek,mt8195-disp-dithermediatek,mt8183-disp-dither7p7c(  pdsi@1c008000(mediatek,mt8195-dsimediatek,mt8183-dsi77c((*Tenginedigitalhs  Pdphy disableddsc@1c009000mediatek,mt8195-disp-dsc77c( dsi@1c012000(mediatek,mt8195-dsimediatek,mt8183-dsi7 7c((+Tenginedigitalhs  Pdphy disabledmerge@1c014000mediatek,mt8195-disp-merge7@7c( @dp-intf@1c015000mediatek,mt8195-dp-intf7Pc(,(!Tpixelenginepllokayportendpoint (mutex@1c016000mediatek,mt8195-disp-mutex7`7c( ` Ularb@1c018000mediatek,mt8195-smi-larb7  c((((%  Tapbsmigals7larb@1c019000mediatek,mt8195-smi-larb7  c((% % Tapbsmigals7syscon@1c100000mediatek,mt8195-vdosys1syscon7  VD.smi@1c01b000mediatek,mt8195-smi-common-vdo7 c(%(&()($Tapbsmigals0gals17iommu@1c01f000mediatek,mt8195-iommu-vdo78 c('Tbclk7mutex@1c101000mediatek,mt8195-disp-mutex77c.  larb@1c102000mediatek,mt8195-smi-larb7   c... Tapbsmigals7larb@1c103000mediatek,mt8195-smi-larb70  c..%  Tapbsmigals7dma-controller@1c104000mediatek,mt8195-vdo1-rdma7@c.7 @ @ dma-controller@1c105000mediatek,mt8195-vdo1-rdma7Pc.7 ` P dma-controller@1c106000mediatek,mt8195-vdo1-rdma7`c.7 A ` dma-controller@1c107000mediatek,mt8195-vdo1-rdma7pc.7 a p dma-controller@1c108000mediatek,mt8195-vdo1-rdma7c.7 B  dma-controller@1c109000mediatek,mt8195-vdo1-rdma7c.7 b  dma-controller@1c10a000mediatek,mt8195-vdo1-rdma7c.7 C  dma-controller@1c10b000mediatek,mt8195-vdo1-rdma7c.7 c  vpp-merge@1c10c000mediatek,mt8195-disp-merge7c. .Tmergemerge_async7  8*.vpp-merge@1c10d000mediatek,mt8195-disp-merge7c. .Tmergemerge_async7  8*.vpp-merge@1c10e000mediatek,mt8195-disp-merge7c. .Tmergemerge_async7  8*.vpp-merge@1c10f000mediatek,mt8195-disp-merge7c. .Tmergemerge_async7  8*.vpp-merge@1c110000mediatek,mt8195-disp-merge7c. .Tmergemerge_async7  L*.dp-intf@1c113000mediatek,mt8195-dp-intf707c./.!Tpixelenginepllokayportendpoint (hdr-engine@1c114000mediatek,mt8195-disp-ethdrp7@Pp4Qmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsp @Pphc.%. .#.!.$.".1.&.'.(.).*"Tmixervdo_fe0vdo_fe1gfx_fe0gfx_fe1vdo_beadl_dsvdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncethdr_top7 de(*.3.4.5.6.7E1vdo_fe0_asyncvdo_fe1_asyncgfx_fe0_asyncgfx_fe1_asyncvdo_be_asyncedp-tx@1c500000mediatek,mt8195-edp-tx7Pp|dp_calibration_data7 cokaydefaultports+port@07endpoint (port@17endpoint t (aux-buspanel edp-panel  portendpoint (dp-tx@1c600000mediatek,mt8195-dp-tx7`p|dp_calibration_data7 cokay defaultports+port@07endpoint (port@17endpoint tthermal-zonescpu0-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalcooling-mapsmap0 0 cpu1-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalcooling-mapsmap0 0 cpu2-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalcooling-mapsmap0 0 cpu3-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalcooling-mapsmap0 0 cpu4-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalcooling-mapsmap0 0 cpu5-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalcooling-mapsmap0 0 cpu6-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalcooling-mapsmap0 0 cpu7-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalcooling-mapsmap0 0 vpu0-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalvpu1-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalgpu-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalgpu1-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalvdec-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalimg-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalinfra-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalcam0-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalcam1-thermal   tripstrip-alert L Epassivetrip-crit   Ecriticalsoc-area-thermal   tripstrip-crit H   Ecriticalpmic-area-thermal   tripstrip-crit H   Ecriticalbacklight-lcd0pwm-backlight @  R- D  chosenIserial0:115200n8memory@40000000+memory7@regulator-pp3300-disp-xregulator-fixedpp3300_disp_x 2Z%2Z= U h7defaultmjregulator-pp3300-ldo-z5regulator-fixedpp3300_ldo_z5Yx 2Z%2Zmkregulator-pp3300-s3regulator-fixed pp3300_s3Yx 2Z%2Zmjgregulator-pp3300-z2regulator-fixed pp3300_z2Yx 2Z%2Zmjregulator-pp4200-z2regulator-fixed pp4200_z2Yx @@%@@mregulator-pp5000-s5regulator-fixed pp5000_s5Yx LK@%LK@mregulator-ppvar-sysregulator-fixed ppvar_sysYxthermal-sensor-t1generic-adc-thermalsensor-channelx~%':[N au0@] P`Gp$8L_}sk\(OD8;3H,thermal-sensor-t2generic-adc-thermalsensor-channelx~%':[N au0@] P`Gp$8L_}sk\(OD8;3H,regulator-5v0-usb-vbusregulator-fixed usb-vbus LK@%LK@UYKreserved-memory+memory@50000000shared-dma-pool7P4memory@60000000shared-dma-pool7`;memory@60d80000shared-dma-pool7`=memory@60e80000shared-dma-pool7`(:rt1019prealtek,rt1019prt1019p default d disabled compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typedp-intf0dp-intf1gce0gce1ethdr0mutex0mutex1merge1merge2merge3merge4merge5vdo1-rdma0vdo1-rdma1vdo1-rdma2vdo1-rdma3vdo1-rdma4vdo1-rdma5vdo1-rdma6vdo1-rdma7i2c0i2c1i2c2i2c3i2c4i2c5i2c7mmc0mmc1serial0device_typeregenable-methodperformance-domainsclock-frequencycapacity-dmips-mhzcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cache#cooling-cellscpu-supplyphandlecpuentry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedinterruptscpusstatusnum-channelswakeup-delay-msmediatek,platformmediatek,adspmediatek,dai-linkpinctrl-namespinctrl-0audio-routinglink-namemediatek,clk-providersound-dai#clock-cellsclocksclock-divclock-multclock-output-names#performance-domain-cellsopp-sharedopp-hzopp-microvoltrangesdma-ranges#interrupt-cells#redistributor-regionsinterrupt-controllermediatek,broken-save-restore-fwaffinity#reset-cellsreg-namesgpio-controller#gpio-cellsgpio-rangesmediatek,rsel-resistance-in-si-unitgpio-line-namespinmuxinput-enablebias-pull-upbias-disabledrive-strength-microampdrive-strengthbias-pull-downoutput-highoutput-low#power-domain-cellsdomain-supplyclock-namesmediatek,infracfgmediatek,disable-extrstassigned-clocksassigned-clock-parentsinterrupts-extended#io-channel-cellsmediatek,dmic-modemediatek,mic-type-0regulator-nameregulator-min-microvoltregulator-max-microvoltregulator-enable-ramp-delayregulator-always-onregulator-ramp-delayregulator-allowed-modesregulator-compatible#iommu-cells#mbox-cellsfirmware-namememory-regionmediatek,rpmsg-namepower-domainsmbox-namesmboxesmediatek,topckgenresetsreset-namesmediatek,etdm-in2-cowork-sourcemediatek,etdm-out2-cowork-sourcemediatek,pad-selectspi-max-frequencywakeup-sourcegoogle,remote-bussbs,i2c-retry-countsbs,poll-retry-countpower-roledata-roletry-power-rolekeypad,num-rowskeypad,num-columnsgoogle,needs-ghost-filterlinux,keymapfunction-row-physmapnvmem-cellsnvmem-cell-names#thermal-sensor-cells#pwm-cellsinterrupt-namesmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrsnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightsnps,priorityphysmediatek,syscon-wakeupdr_modevusb33-supplyrx-fifo-depthvbus-supplybus-widthcap-mmc-highspeedcap-mmc-hw-reseths400-ds-delaymmc-hs200-1_8vmmc-hs400-1_8vno-sdiono-sdnon-removablepinctrl-1vmmc-supplyvqmmc-supplycap-sd-highspeedcd-gpiosno-mmcsd-uhs-sdr50sd-uhs-sdr104mediatek,u3p-dis-mskusb2-lpm-disablebus-rangeiommu-mapiommu-map-maskphy-namesinterrupt-map-maskinterrupt-mapspi-rx-bus-widthspi-tx-bus-widthbits#phy-cellsi2c-scl-internal-delay-nsvcc-supply#sound-dai-cellsrealtek,jd-srcAVDD-supplyMICVDD-supplyVBAT-supplyrealtek,amic-delay-msreset-gpiossound-name-prefixhid-descr-addrpost-power-on-delay-msvdd-supplyoperating-points-v2power-domain-namesmali-supplymediatek,gce-client-regmediatek,gce-eventsmediatek,scpiommus#dma-cellsmediatek,smimediatek,larb-idmediatek,larbsremote-endpointmediatek,merge-mutemediatek,merge-fifo-enmax-linkrate-mhzdata-lanespower-supplybacklightpolling-delaypolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-devicebrightness-levelsdefault-brightness-levelenable-gpiosnum-interpolated-stepspwmsstdout-pathenable-active-highgpiovin-supplyregulator-boot-onio-channelsio-channel-namestemperature-lookup-tableno-maplabelsdb-gpios